Time-space tiling with tile-level parallelism for the 3D FDTD method

Our aim in this work is to improve the performance of the multi-threaded 3D FDTD solver using time-space tiling techniques that enable tile-level parallelization. The implementation of tile-level parallelization that we have used is based on the so-called diamond tiling technique. In this paper, we present a systematic manner for introducing time-space tiling techniques into the 3D FDTD solver and compare four different approaches. Our performance evaluation on a state-of-the-art multi-core processor demonstrated the effectiveness of the time-space tiling techniques with tile-level parallelism for the 3D FDTD method. For the problem with 2003 grid points, our implementation with two-dimensional tile-level parallelism achieved a speedup of 1.88 times over the naive implementation, while for the problem of 3003 grid points, our implementation with one-dimensional tile-level parallelism showed a speedup of 2.22 times. Both results are better than the speedup obtained from an implementation with intra-tile parallelization presented in a previous work.