多值逻辑电路多电平逻辑综合的代数划分

Hui Min Wang, Chung-Len Lee, Jwu-E Chen
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引用次数: 5

摘要

提出了多值逻辑的多层逻辑综合的代数划分概念。首先,建立了基于基本门集的MVL代数除法程序。通过在除法运算中引入“同”和“互补”两个MVL布尔性质,进一步将该过程改进为混合代数除法过程,可以获得更高效的代数除法,便于MVL函数的多级逻辑综合。实验结果表明,一个MVL函数的多级实现成本平均比两级实现成本节约30.1%,改进的混合代数除法比代数除法成本节约19.4%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Algebraic division for multilevel logic synthesis of multi-valued logic circuits
Presents the concept of algebraic division for multilevel logic synthesis of multi-valued logic (MVL). At first, an MVL algebraic division procedure is developed based on a basic set of gates. By introducing two MVL Boolean properties: "identical" and "complementary" into the division operation, the procedure is further improved to be a mix-algebraic division procedure, which can obtain more efficient algebraic division to facilitate multilevel logic synthesis of MVL functions. Experimental results show that, in average, the multilevel implementation cost for an MVL function can have 30.1% cost saving over the two-level implementation, and the improved mix-algebraic division procedure can have 19.4% cost saving over the algebraic division procedure.<>
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