I. Budihardjo, P. Lauritzen, K. Wong, R. Darling, H. Mantooth
{"title":"定义功率半导体器件的标准性能等级","authors":"I. Budihardjo, P. Lauritzen, K. Wong, R. Darling, H. Mantooth","doi":"10.1109/IAS.1995.530423","DOIUrl":null,"url":null,"abstract":"Model validation for power semiconductor devices is classified into five levels with model performance features and applications defined for each level. The five levels for each device correspond to: basic, accurate, thermal, failure and degradation models. Whenever they exist, examples of device models are identified for each power semiconductor device.","PeriodicalId":117576,"journal":{"name":"IAS '95. Conference Record of the 1995 IEEE Industry Applications Conference Thirtieth IAS Annual Meeting","volume":"65 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"Defining standard performance levels for power semiconductor devices\",\"authors\":\"I. Budihardjo, P. Lauritzen, K. Wong, R. Darling, H. Mantooth\",\"doi\":\"10.1109/IAS.1995.530423\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Model validation for power semiconductor devices is classified into five levels with model performance features and applications defined for each level. The five levels for each device correspond to: basic, accurate, thermal, failure and degradation models. Whenever they exist, examples of device models are identified for each power semiconductor device.\",\"PeriodicalId\":117576,\"journal\":{\"name\":\"IAS '95. Conference Record of the 1995 IEEE Industry Applications Conference Thirtieth IAS Annual Meeting\",\"volume\":\"65 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IAS '95. Conference Record of the 1995 IEEE Industry Applications Conference Thirtieth IAS Annual Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IAS.1995.530423\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IAS '95. Conference Record of the 1995 IEEE Industry Applications Conference Thirtieth IAS Annual Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IAS.1995.530423","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Defining standard performance levels for power semiconductor devices
Model validation for power semiconductor devices is classified into five levels with model performance features and applications defined for each level. The five levels for each device correspond to: basic, accurate, thermal, failure and degradation models. Whenever they exist, examples of device models are identified for each power semiconductor device.