自动全数字锁相环系统设计与优化工具

Abdelrahman S. Moustafa, H. Omran, K. Sharaf
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引用次数: 0

摘要

介绍了一种全数字锁相环(ADPLL)系统的自动化设计与优化工具。ADPLL系统的设计目标是利用解析噪声模型和相位噪声仿真结果确定ADPLL各模块的数字环路滤波器(DLF)系数,然后采用进化优化方法对DLF系数进行优化,以实现ADPLL的最佳锁相时间和相位噪声。用该工具设计的ADPLL的系统仿真结果表明,该ADPLL符合系统的要求。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Automatic All-Digital Phase-Locked Loop System Design and optimization Tool
An automated design and optimization tool for all digital phase locked-loop (ADPLL) system is presented in this paper. The ADPLL system design goal is to determine the digital loop filter (DLF) coefficients using analytic noise models and phase noise simulation results for each ADPLL block, then the DLF coefficients are optimized using evolutionary optimization method to achieve the optimum locking time and phase noise of the ADPLL. The system simulation results of the ADPLL designed by the tool show good agreement with the system’s required specifications.
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