高性能DSP专用集成电路的快速周转方法

[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track Pub Date : 1989-01-03 DOI:10.1109/HICSS.1989.47140

P. Ang, P.A. Ruetz

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引用次数: 0

摘要

本文描述了一种在高性能数字信号处理器系列设计中取得成功的方法。它在不牺牲性能的情况下提供了短设计周期的优势。该方法依赖于具有良好特征的标准单元库、精确的门级模拟器、用于架构评估的行为模拟器以及用于通用数字信号处理算子(如乘法器和加法器)的模块生成器。该方法具有灵活性，可以将逻辑描述重新定位为基于数组的、基于单元格的，甚至是完全自定义的物理实现。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A methodology for quick turn-around of high performance DSP ASICS

An approach that has been successfully in the design of a family of high-performance digital signal processors is described. It offers the advantage of a short design cycle without sacrificing performance. The method relies on the availability of a well-characterized standard cell library, an accurate gate-level simulator, a behavioral simulator for architectural evaluations, and module generators for generic digital signal processing operators such as multipliers and adders. The method has the flexibility of being able to retarget the logic description into either an array-based, cell-based, or even full-custom physical implementation.<>

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来源期刊

[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track

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