Can Functional Test Achieve Low-cost Full Coverage of NoC Faults?

The advent of the system-on-chip (SoC) technology and the integration of multiple cores and Networkon-Chip (NoC) on a single die brought new challenges in terms of testability. Defining an efficient and complete test strategy for such a new kind of system architecture is still an open problem. The test of NoC-based multicore chips is generally divided into the test of cores and the test of the communication infrastructure (network). The test of cores is usually based on the reuse of the NoC as Test Access Mechanism (TAM) to reduce area overhead and test time. As a result, the testing of the communication infrastructure is essential to guarantee the reliability of the entire system. Test approaches for the detection of faults in the communication infrastructure have based their strategies on functional, scan or BIST-based testing. All existing approaches complement each other, in the sense that none can fully cover the faults that may affect all routers and interconnects of the network. Some of the existing approaches target faults in the routers, while others cope with faults on interconnects. The refereed fault models differ from one work to another, both in terms of abstraction level (functional, RT or logic level) and of covered parts (FIFOs, registers, multiplexers, routing logic, interconnect links). This talk focuses on the functional testing of the NoC infrastructure. Herein, we are seeking for the integration of the test of interconnects and routers, at the lowest possible cost. Therefore, a manufacturing test strategy is proposed, that considers more realistic, logic level fault models, and attempts to fully cover faults that affect both the router logic and the communication channel wires. A functional-based approach is preferred, to reduce NoC re-design costs and to provide at-speed testing. However, scan and BISTbased approaches may be required to enhance both fault coverage and test application time.