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引用次数: 3
摘要
在硅片上研究了40 v CMOS工艺中器件结构和布局参数对ESD稳健性的影响。从实验结果来看，漏极区没有漂移植入的高压mosfet比漏极区有漂移植入的高压mosfet具有更好的tlp测量It2和ESD鲁棒性。此外，HV mosfet的It2和ESD水平可以随着漏极扩散到多栅极的布局间距的增加而增加
ESD Robustness of 40-V CMOS Devices With/Without Drift Implant
The dependences of device structures and layout parameters on ESD robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the high-voltage (HV) MOSFETs without drift implant in the drain region have better TLP-measured It2 and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased
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