并行神经网络实现的硬件方面

I. Kouretas, Vassilis Paliouras
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引用次数: 0

摘要

本文提出了一种并行神经网络结构,其目标是在低资源设备上实现高效的硬件实现。在介绍了所提出的技术之后,将新概念应用于两个基本函数逼近示例,即cos(x)和sin(x)。给出了定量结果,并从精度和硬件复杂性方面进行了讨论。在考虑针对边缘设备的低功耗和高性能硬件实现时,所提出的技术取得了令人满意的结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Hardware Aspects of Parallel Neural Network Implementation
In this paper a parallel neural network architecture is proposed targeting efficient hardware implementation on low-resource devices. Following the introduction of the proposed technique, the novel concept is applied on two basic function approximation examples namely cos(x) and sin(x). Quantitative results are offered and discussed in terms of accuracy and hardware complexity. It is shown that the proposed technique achieves promising results when considering low-power and high-performance hardware implementations targeted to edge devices.
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