A data-flow oriented co-design for reconfigurable systems

Multi FPGA systems are mainly composed of programmable logic devices and external memory. Up to date FPGAs also contain embedded static RAMs, which have shorter access time than the external SRAMs. The paper presents a dataflow oriented algorithm that makes use of the small embedded memories as local caches for data processing. The algorithm offers a high level of parallelism and efficient use of processing resources. This is done in the context of hardware-software co-design. The objective is to automatically implement parts of C code requiring high processing rates on a reconfigurable system. An example of implementation on a 400 Kgates 8 Mbytes multi FPGA system is described.