Simulation study of 25 nm PMOS FinFET fabrication with silicon co-implant

Silicon co-implantation into PMOS FinFET fabrication is presented. The co-implantation method is applied at the source and drain to enhance transportation properties of the devices. The device is fabricated using an industry oriented tool, Sentaurus TCAD. Performance assessment is performed on two electrical parameters, which are threshold voltage and driving current. The simulation results show that these parameters are strongly dependent on the co-implantation level. Threshold voltage is reduced with energy implantation of Silicon doped but increased with silicon implant dose concentration. The silicon co-implantation also positively affects the on-current as the on-state current significantly increased.