{"title":"基于90nm CMOS的6位宽带低群延迟变增益放大器","authors":"M. Parlak, M. Matsuo, J. Buckwalter","doi":"10.1109/SIRF.2012.6160121","DOIUrl":null,"url":null,"abstract":"This paper presents the design and implementation of a differential 6-bit variable gain amplifier (VGA) with low group delay imbalance over 64 gain states. Low group delay imbalance is crucial for wireless positioning technologies such as ranging biosensors. The VGA is designed to track the Friss loss and the gain variation is achieved using bias current steering. Two cascaded linear-in-magnitude stages provide 52 dB of gain control. The measured maximum group delay variation is 50 ps over 64 states. The input P1dB gain compression point ranges between -26 dBm and -15 dBm. The saturated output power is -5 dBm for 64 gain states. The VGA is implemented in a 90nm CMOS process and the chip size is 0.035mm2. The VGA consumes 14 mA from a 1.2 V supply excluding the buffer power consumption.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A 6-bit wideband variable gain amplifier with low group delay variation in 90nm CMOS\",\"authors\":\"M. Parlak, M. Matsuo, J. Buckwalter\",\"doi\":\"10.1109/SIRF.2012.6160121\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design and implementation of a differential 6-bit variable gain amplifier (VGA) with low group delay imbalance over 64 gain states. Low group delay imbalance is crucial for wireless positioning technologies such as ranging biosensors. The VGA is designed to track the Friss loss and the gain variation is achieved using bias current steering. Two cascaded linear-in-magnitude stages provide 52 dB of gain control. The measured maximum group delay variation is 50 ps over 64 states. The input P1dB gain compression point ranges between -26 dBm and -15 dBm. The saturated output power is -5 dBm for 64 gain states. The VGA is implemented in a 90nm CMOS process and the chip size is 0.035mm2. The VGA consumes 14 mA from a 1.2 V supply excluding the buffer power consumption.\",\"PeriodicalId\":339730,\"journal\":{\"name\":\"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIRF.2012.6160121\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIRF.2012.6160121","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 6-bit wideband variable gain amplifier with low group delay variation in 90nm CMOS
This paper presents the design and implementation of a differential 6-bit variable gain amplifier (VGA) with low group delay imbalance over 64 gain states. Low group delay imbalance is crucial for wireless positioning technologies such as ranging biosensors. The VGA is designed to track the Friss loss and the gain variation is achieved using bias current steering. Two cascaded linear-in-magnitude stages provide 52 dB of gain control. The measured maximum group delay variation is 50 ps over 64 states. The input P1dB gain compression point ranges between -26 dBm and -15 dBm. The saturated output power is -5 dBm for 64 gain states. The VGA is implemented in a 90nm CMOS process and the chip size is 0.035mm2. The VGA consumes 14 mA from a 1.2 V supply excluding the buffer power consumption.