{"title":"冗余二进制乘法器的一种备选方案","authors":"Chip-Hong Chang, Yajuan He, J. Gu","doi":"10.1109/APCCAS.2004.1412684","DOIUrl":null,"url":null,"abstract":"This work addresses the feasibility of re-engineering the multiplier architecture that is based on a new redundant number representation called the non-carry-propagation (NCP) format to avoid carry propagation. The preliminary theoretical assessments and simulation result show that this multiplier possesses certain revelatory features that make it a potential alternative approach to conventional redundant binary multiplier. The characteristics of NCP number and the structure of NCP adders array are analyzed. A new reverse converter was also proposed to simplify the converter circuit that converts the final redundant binary number into the corresponding 2's complement number. A recommended gate-level implementation of the multiplier based on this new architecture is also presented.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"An alternative scheme of redundant binary multiplier\",\"authors\":\"Chip-Hong Chang, Yajuan He, J. Gu\",\"doi\":\"10.1109/APCCAS.2004.1412684\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work addresses the feasibility of re-engineering the multiplier architecture that is based on a new redundant number representation called the non-carry-propagation (NCP) format to avoid carry propagation. The preliminary theoretical assessments and simulation result show that this multiplier possesses certain revelatory features that make it a potential alternative approach to conventional redundant binary multiplier. The characteristics of NCP number and the structure of NCP adders array are analyzed. A new reverse converter was also proposed to simplify the converter circuit that converts the final redundant binary number into the corresponding 2's complement number. A recommended gate-level implementation of the multiplier based on this new architecture is also presented.\",\"PeriodicalId\":426683,\"journal\":{\"name\":\"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-12-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCCAS.2004.1412684\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.2004.1412684","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An alternative scheme of redundant binary multiplier
This work addresses the feasibility of re-engineering the multiplier architecture that is based on a new redundant number representation called the non-carry-propagation (NCP) format to avoid carry propagation. The preliminary theoretical assessments and simulation result show that this multiplier possesses certain revelatory features that make it a potential alternative approach to conventional redundant binary multiplier. The characteristics of NCP number and the structure of NCP adders array are analyzed. A new reverse converter was also proposed to simplify the converter circuit that converts the final redundant binary number into the corresponding 2's complement number. A recommended gate-level implementation of the multiplier based on this new architecture is also presented.