System Level Testing via TLM 2.0 Debug Transport Interface

With the rapid increase in the complexity of digital circuits, the design abstraction level has to grow to face the new needs of system designers in the early phases of the design process. Along with this evolution, testing and test facilities should be improved in the early stages of the design to provide the architecture with functional test facilities to be later synthesized testing infrastructures according to designer’s requirements. These test infrastructures could be translated, into testing facilities at lower levels of abstraction, from which automatic synthesis tools are available. Starting from the increasing use of TLM in hardware design industry, the paper aims at providing a mechanism to fill the gap between the design abstraction level and the level in which testing methodologies are applied. To do the job, the TLM 2.0 “debug transport interface” is used and methods are introduced to synthesize it into known test access methods at RTL.