Detection performance and systolic architectures for OS-CFAR detectors

Performance analyses and architectures for the order statistic detectors (OSD) in radar signal processing are presented. Based on an analytical model in which the number of interfering targets is random, the detectability is evaluated. It is shown that the system is much more susceptible to a random degree of interference than merely a fixed number of interferers. In addition, a relationship between binary integration and order statistics suggests a novel implementation. By showing that M-out-of-N binary integration is equivalent to selecting the (N+1-M)/sup st/ order statistic, the OSD(R,K) that uses R reference cells using only R+1 comparators is implemented. A systolic architecture is presented that can implement this approach with the advantages of a regular, parallel, and fully pipelined structure.<>