Parallel Segmentation Algorithm Based on Computation Front for Numerical Acceleration in Electrical Drive Real-time Simulation

HIL (Hardware in Loop) is an efficient and convenient tool for the test and verification of electrical drive system which requires high reliability and safety. With the application of high-frequency SiC inverter, the time scale is reduced below μs-level, as a result, the computation speed becomes an unignorable challenge for HIL system because of the strict real-time constraint. Under these circumstances, the development and applications of hardware with parallel process structure such as FPGA is a solution for computation acceleration on the hardware level. On the software level, unfortunately, most of the state-of-the-art numerical models and algorithms are based on sequential mechanism, as a result, the parallel algorithm is demanded to achieve further acceleration. This paper proposes a general method based on computation front to design parallel algorithm for real-time simulation. By analyzing numerical flow diagram, numerical integration method is optimized to realize acceleration derived from parallel segmentation. Simulation results show that good acceleration effect without great accuracy reduction is achieved.