A. Verdant, A. Dupret, M. Tchagaspanian, A. Peizerat
{"title":"用于三维CMOS图像传感器的计算式SAR ADC","authors":"A. Verdant, A. Dupret, M. Tchagaspanian, A. Peizerat","doi":"10.1109/NEWCAS.2012.6329025","DOIUrl":null,"url":null,"abstract":"The architecture and simulation of a Computational SAR ADC (C-SAR) dedicated to the processing of image descriptors for a 3D CMOS image sensor are reported here. The differential charge sharing architecture enables to A/D convert the convolution of multiple binary weighted pixels signals on multi-scale kernels. The CMOS image sensor is constituted of two tiers. An array of C-SAR is implemented on the bottom layer. Each C-SAR is associated to a square of 8×8 pixels on the top layer, with a pitch of 10μm and a fill factor of 80%. With regard to a standard differential SAR ADC, only multiplexing facilities are added in the C-SAR. This area over cost is 10 times lower than the surface induced by the memory required for a counterpart digital architecture. The total noise of 458μVRMS simulated at transistor level on a 65nm technology enables to reach a processing resolution of 9 signed bits on 0.5V pixels dynamic. As the processing is done within the conversion stage, no additional time is needed. With a power consumption of 400μW and a bandwidth of 1 mega-convolution per second, this processing architecture outputs a FOM of 6.25pJ/pixel.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Computational SAR ADC for a 3D CMOS image sensor\",\"authors\":\"A. Verdant, A. Dupret, M. Tchagaspanian, A. Peizerat\",\"doi\":\"10.1109/NEWCAS.2012.6329025\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The architecture and simulation of a Computational SAR ADC (C-SAR) dedicated to the processing of image descriptors for a 3D CMOS image sensor are reported here. The differential charge sharing architecture enables to A/D convert the convolution of multiple binary weighted pixels signals on multi-scale kernels. The CMOS image sensor is constituted of two tiers. An array of C-SAR is implemented on the bottom layer. Each C-SAR is associated to a square of 8×8 pixels on the top layer, with a pitch of 10μm and a fill factor of 80%. With regard to a standard differential SAR ADC, only multiplexing facilities are added in the C-SAR. This area over cost is 10 times lower than the surface induced by the memory required for a counterpart digital architecture. The total noise of 458μVRMS simulated at transistor level on a 65nm technology enables to reach a processing resolution of 9 signed bits on 0.5V pixels dynamic. As the processing is done within the conversion stage, no additional time is needed. With a power consumption of 400μW and a bandwidth of 1 mega-convolution per second, this processing architecture outputs a FOM of 6.25pJ/pixel.\",\"PeriodicalId\":122918,\"journal\":{\"name\":\"10th IEEE International NEWCAS Conference\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-06-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"10th IEEE International NEWCAS Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NEWCAS.2012.6329025\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"10th IEEE International NEWCAS Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NEWCAS.2012.6329025","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The architecture and simulation of a Computational SAR ADC (C-SAR) dedicated to the processing of image descriptors for a 3D CMOS image sensor are reported here. The differential charge sharing architecture enables to A/D convert the convolution of multiple binary weighted pixels signals on multi-scale kernels. The CMOS image sensor is constituted of two tiers. An array of C-SAR is implemented on the bottom layer. Each C-SAR is associated to a square of 8×8 pixels on the top layer, with a pitch of 10μm and a fill factor of 80%. With regard to a standard differential SAR ADC, only multiplexing facilities are added in the C-SAR. This area over cost is 10 times lower than the surface induced by the memory required for a counterpart digital architecture. The total noise of 458μVRMS simulated at transistor level on a 65nm technology enables to reach a processing resolution of 9 signed bits on 0.5V pixels dynamic. As the processing is done within the conversion stage, no additional time is needed. With a power consumption of 400μW and a bandwidth of 1 mega-convolution per second, this processing architecture outputs a FOM of 6.25pJ/pixel.