同步器电阻性开路缺陷分析

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI:10.1109/DFT.2009.34

Hyoung-Kook Kim, W. Jone, Laung-Terng Wang

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引用次数: 4

摘要

本文对由两个三维触发器实现的同步器中的开路缺陷进行了故障建模和分析。将开放缺陷注入同步器的任何节点，并使用HSPICE进行电路分析。此分析的主要目的是找到所有可能由开放缺陷在同步器中发生的错误。所得结果可用于开发用同步器实现的不同时钟域间接口电路的测试方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Analysis of Resistive Open Defects in a Synchronizer

This paper presents fault modeling and analysis for open defects in a synchronizer that is implemented by two D flip-flops. Open defects are injected into any node of the synchronizer, and HSPICE is used to perform circuit analysis. The major purpose of this analysis is to find all possible faults that might occur in the synchronizer by open defects. The results obtained can be used to develop methods for testing the interfacing circuits between different clock domains which are implemented with the synchronizer.

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2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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