The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.最新文献

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A low-cost and application-driven digital signal processor for speech/audio processing 用于语音/音频处理的低成本和应用驱动的数字信号处理器
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412773
Jen-Feng Chung, Chin-Teng Lin
{"title":"A low-cost and application-driven digital signal processor for speech/audio processing","authors":"Jen-Feng Chung, Chin-Teng Lin","doi":"10.1109/APCCAS.2004.1412773","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412773","url":null,"abstract":"In this paper, a new application-driven digital signal processor, called LASP24 (low-cost application-driven speech processor, 24-bit data width), for speech and audio signal processing is designed. Two applications, MELP and reverberation algorithms, are performed on LASP24. The developed emulator can quickly verify these two algorithms. The design has been integrated in the total area of 6.5 mm2 by using UMC 0.18mum 1P6M technology and fabricated. The maximum clock frequency is about 100 MHz with a single 1.8V supply","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128672638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Efficient weighted L/sub P/ algorithm for the design of low-pass FIR filters with some closed-form derivations 一种有效的加权L/sub P/算法,用于低通FIR滤波器的设计
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412780
Yue-Dar Jou, Tain-Shou Nien
{"title":"Efficient weighted L/sub P/ algorithm for the design of low-pass FIR filters with some closed-form derivations","authors":"Yue-Dar Jou, Tain-Shou Nien","doi":"10.1109/APCCAS.2004.1412780","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412780","url":null,"abstract":"In this paper, an efficient iterative reweighted least-squares (IRLS) algorithm for the design of LP approximation FIR filters is investigated. The optimal filter coefficients are obtained by iteratively solving a system of linear equations whose associated matrix can be further simplified as closed-form expressions and pre-calculated as the filter is specified. Simulation results indicate the excellent performance of the proposed algorithm has a complexity of O(N2)","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122406647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance bounds for block transmission system 块传输系统的性能界限
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412804
F. Ghani
{"title":"Performance bounds for block transmission system","authors":"F. Ghani","doi":"10.1109/APCCAS.2004.1412804","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412804","url":null,"abstract":"The paper presents an analysis of the Block Transmission System (BTS) that has recently been proposed for mobile channels. Decision boundaries and decision regions have been obtained for the block linear equalizer and the optimum detector for the system. These provide the lower and upper bounds to the performance of the BTS in the presence of additive white Gaussian noise. It is shown that despite of the reduced transmission efficiency the performance of the block linear equalizer is comparable with that of the transversal equalizer and makes it suitable for use in mobile systems","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122243105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Digital image watermarking approach based on lapped orthogonal transform 基于重叠正交变换的数字图像水印方法
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1413084
Feng-Hsing Wang, Jeng-Shyang Pan, L. Jain, H.-C. Huang
{"title":"Digital image watermarking approach based on lapped orthogonal transform","authors":"Feng-Hsing Wang, Jeng-Shyang Pan, L. Jain, H.-C. Huang","doi":"10.1109/APCCAS.2004.1413084","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1413084","url":null,"abstract":"A new watermarking approach based on lapped orthogonal transform (LOT) is proposed. It provides better imperceptibility by reducing the blocking effects which exist in most block-based image coding transforms like JPEG. The proposed scheme performs the LOT to the cover image, modifies the LOT coefficients to hide the watermark bits according to the given user-key, and executes the inverse LOT to generate a watermarked image. It requires no original cover image to be introduced during extraction, and it has strong robustness under the JPEG attacks.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122329410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 1V 2.4GHz CMOS power amplifier with integrated diode linearizer 集成二极管线性化器的1V 2.4GHz CMOS功率放大器
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412703
Kun-Yi Lin, R. Weng, C. Hsiao, H. Wei
{"title":"A 1V 2.4GHz CMOS power amplifier with integrated diode linearizer","authors":"Kun-Yi Lin, R. Weng, C. Hsiao, H. Wei","doi":"10.1109/APCCAS.2004.1412703","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412703","url":null,"abstract":"A low voltage CMOS power amplifier with integrated diode linearization technique is proposed. It is designed for 2.4 GHz Bluetooth applications. The power amplifier is simulated with UMC 0.18/spl mu/m CMOS technology. Under 1V supply voltage, PA can deliver 20 dBm output power with 51% power-added-efficiency. At 2.4 GHz, the reverse isolation coefficient S12 is -27.5 dB.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127184034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Comparison of the noise immunity of a LED-based multiband optoelectronic sensor when using FDMA and CDMA to code the excitation source 采用FDMA和CDMA编码激励源时led多波段光电传感器的抗噪性比较
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1413073
M. Boukadoum, K. Tabari, A. Bensaoula, D. Starikov
{"title":"Comparison of the noise immunity of a LED-based multiband optoelectronic sensor when using FDMA and CDMA to code the excitation source","authors":"M. Boukadoum, K. Tabari, A. Bensaoula, D. Starikov","doi":"10.1109/APCCAS.2004.1413073","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1413073","url":null,"abstract":"We compare the noise immunity of the LED-based optoelectronic front end of a multiband spectral detection and analysis device when using FDMA and CDMA coding for the excitation source. Our results are that the two coding schemes offer comparable performance at low signal-over-noise levels, but that the CDMA approach offers a much better noise immunity in noisy environments. It is thus a much better alternative to drive the excitation source than the more common synchronous modulation approach that underlines FDMA.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"438 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124256476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Effect of non-uniform traffic distributions on load balancing in cellular CDMA systems 非均匀业务分布对蜂窝CDMA系统负载均衡的影响
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412997
K. Chu, F. Lin
{"title":"Effect of non-uniform traffic distributions on load balancing in cellular CDMA systems","authors":"K. Chu, F. Lin","doi":"10.1109/APCCAS.2004.1412997","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412997","url":null,"abstract":"This paper presents a load balancing model to investigate the effect of non-uniform traffic distributions on load balancing in CDMA system. Applying two traffic models on non-uniform traffic distributions, the impact of traffic non-uniformity on system load balancing is compared with uniform distributions. To evaluate the model, we define both load balancing factor (LBF) and load balancing coefficient (LBC). Results indicate that the more offered traffic is easier to achieving load balancing than the less offered traffic.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126217161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS infrared optical preamplifier with a variable-gain transimpedance amplifier 一种带可变增益跨阻放大器的CMOS红外光学前置放大器
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412745
R. Y. Chen, Chih-Yuan Hung, Tsung-Shuen Hung
{"title":"A CMOS infrared optical preamplifier with a variable-gain transimpedance amplifier","authors":"R. Y. Chen, Chih-Yuan Hung, Tsung-Shuen Hung","doi":"10.1109/APCCAS.2004.1412745","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412745","url":null,"abstract":"A CMOS infrared wireless optical receiver front-end is described. A feedback analysis is carried out for the design of a stable variable-gain transimpedance feedback amplifier. A current-mode amplifier, exhibiting a low input resistance and a high output resistance, is designed. The current amplifier is employed as the feedforward gain element of a variable-gain fully-differential transimpedance feedback amplifier. For an infrared wireless optical receiver front-end employing the transimpedance amplifier, the optical preamplifier achieves a transimpedance gain of 87dB/spl Omega/, a bandwidth of 135MHz with a 5pF photodiode capacitance, and a power consumption of 28mW.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129061515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A new dynamic scaling FFT processor 一种新型动态缩放FFT处理器
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412793
Yu-Wei Lin, Chen-Yi Lee
{"title":"A new dynamic scaling FFT processor","authors":"Yu-Wei Lin, Chen-Yi Lee","doi":"10.1109/APCCAS.2004.1412793","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412793","url":null,"abstract":"A new FFT processor with radix-8 algorithm and novel matrix buffer is presented in this paper. About 64 K bit memory can be saved in 8 K-point FFT by new dynamic scaling approach. Moreover, with data scheduling and pre-fetched buffering, single-port memory can be adopted in our FFT processor. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18 /spl mu/m CMOS process with core area of 4.84 mm/sup 2/ and consumes only 25.2 mW at 20 MHz.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"16 5-6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132845774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Two efficient area reduction methods for implementations of the Rijndael advanced encryption standard 实现Rijndael高级加密标准的两种有效的面积缩减方法
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412768
Shen-Fu Hsiao, Ming-Chih Chen
{"title":"Two efficient area reduction methods for implementations of the Rijndael advanced encryption standard","authors":"Shen-Fu Hsiao, Ming-Chih Chen","doi":"10.1109/APCCAS.2004.1412768","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412768","url":null,"abstract":"In this paper, we propose two methods to reduce the area cost of AES chip. The first method combines the SubBytes(), ShiftRows() and MixColumns() transformations in the cipher process, and the InvMixColumns(), InvShiftRows() and InvSubBytes() in the decipher process through the bit-level substitution and minimization. The second method integrates the combined SubBytes()/ShiftRows()/MixColumns() with the InvMixColumns()/InvShiftRows()/InvSubBytes() into a single function unit by sharing the common operations. Experimental results show that our design saves 21 % area cost of the entire AES chip","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"469 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132287545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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