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A rail-to-rail, constant gain CMOS op-amp 一种轨对轨、恒增益CMOS运算放大器
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412742
Yung-Chih Liang, Meng-Lieh Sheu, W. Hsu
{"title":"A rail-to-rail, constant gain CMOS op-amp","authors":"Yung-Chih Liang, Meng-Lieh Sheu, W. Hsu","doi":"10.1109/APCCAS.2004.1412742","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412742","url":null,"abstract":"A rail-to-rail constant gain CMOS operational amplifier was designed by using complementary differential input stage and current compensation skills. The chip was implemented by a 0.35/spl mu/m 1P4M CMOS standard logic process. The measurement results show that the chip can achieve 110dB gain, 13.6MHz bandwidth, and 1.275mW power consumption, when operating at 3V and 35pF load.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126345366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Dynamic modeling of the SRM drive system from a step load change 负载阶跃变化下SRM驱动系统的动态建模
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1413096
J.B. Wang
{"title":"Dynamic modeling of the SRM drive system from a step load change","authors":"J.B. Wang","doi":"10.1109/APCCAS.2004.1413096","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1413096","url":null,"abstract":"In this paper, a dynamic speed loop modeling of a SRM couple DC generator drive system through a perturbation analysis by using a load resistant change is proposed in this paper. Since it is very difficult to decouple torque current command to the nonlinear relationship among generating torque, current and phase inductance of the SRM at different rotor positions. Thus, an alternative scheme is adopted to estimate the dynamic model of the drive system through a step load resistance change. Finally, the performance of the proposed SRM drive system is demonstrated by the some experimental results.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126346905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Memory efficient and low complexity scalable soft VLC decoding for the video transmission 用于视频传输的高效存储和低复杂度可扩展软VLC解码
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412967
Tsu-Ming Liu, Sheng-Zen Wang, Wen-Hsiao Peng, Chen-Yi Lee
{"title":"Memory efficient and low complexity scalable soft VLC decoding for the video transmission","authors":"Tsu-Ming Liu, Sheng-Zen Wang, Wen-Hsiao Peng, Chen-Yi Lee","doi":"10.1109/APCCAS.2004.1412967","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412967","url":null,"abstract":"In this paper, we propose a scalable soft VLC decoder to significantly reduce the complexity. Generally, the soft VLC decoder needs to maintain many states for the correct decoding. Our approach reduces the complexity by reducing the table size. We reduce the table size by merging two symbols with the same prefix into one. Experimental results show that our proposed adaptive scheme can averagely save 15% of memory access compared with the state-of-the-art algorithms. Furthermore, our proposed scalable soft VLC decoder has more than 1 dB PSNR gain as compared with hard decoding","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126414960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Multistate associative memory with parametrically coupled map networks 具有参数耦合映射网络的多状态联想记忆
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1142/S0218127405012673
G. Tanaka, K. Aihara
{"title":"Multistate associative memory with parametrically coupled map networks","authors":"G. Tanaka, K. Aihara","doi":"10.1142/S0218127405012673","DOIUrl":"https://doi.org/10.1142/S0218127405012673","url":null,"abstract":"The present paper proposes two types of multistate associative memory models using circle maps coupled through a parameter in the individual map. Each network utilizes a circle map with a specific bifurcation property as its component and realizes self-organizing chaotic dynamics in a memory association. The performance of the proposed networks is compared with that of a conventional multistate neural network in multistate associative memory tests.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115778224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Adaptive backstepping control with integral action for PWM buck DC-DC converters PWM降压DC-DC变换器的积分自适应反步控制
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1080/02533839.2005.9671072
Shui-Chun Lin, Ching-Chih Tsai
{"title":"Adaptive backstepping control with integral action for PWM buck DC-DC converters","authors":"Shui-Chun Lin, Ching-Chih Tsai","doi":"10.1080/02533839.2005.9671072","DOIUrl":"https://doi.org/10.1080/02533839.2005.9671072","url":null,"abstract":"Abstract This paper develops a novel control methodology for voltage regulation and implementation of a buck DC‐DC converter using a digital signal processor (DSP). Such a converter is modeled as a linear averaged state‐space system model with an adjustable load. An adaptive backstepping voltage regulator is presented based on the measurements of an output voltage and a capacitor current. An approximate averaged circuit model is derived in order to show that the fast and stable mode of the capacitor current can be ignored and the buck DC‐DC converter can be well approximated by the averaged circuit model. With the approximate averaged model, an adaptive backstepping control with integral action is proposed to regulate a stand‐alone buck DC‐DC converter. This proposed control method has been verified by computer simulation and implemented utilizing a stand‐alone digital signal processor (DSP) TMS320C542 from Texas Instruments. Experimental results show that the proposed control method is capable of giving satisfactory voltage regulation performance under a wide range of input voltage variations and load changes.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132076966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Design of 2D FIR digital filters with symmetric properties by genetic algorithm approach 用遗传算法设计二维对称FIR数字滤波器
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412784
Shian-Tang Tzeng
{"title":"Design of 2D FIR digital filters with symmetric properties by genetic algorithm approach","authors":"Shian-Tang Tzeng","doi":"10.1109/APCCAS.2004.1412784","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412784","url":null,"abstract":"Besides the design of quadrantally symmetric linear-phase 2D FIR digital filters, a wide variety of linear-phase 2D filter designs are proposed in this paper. It is shown that there are 16 types of cases to be considered according to the symmetry/antisymmetry of 2D sequences in both directions and their filter lengths (even or odd). The corresponding types of magnitude responses are tabulated into a complete table if these 2D sequences are used to realize 2D FIR digital filters by genetic algorithm (GA) approach","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134290421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Equaripple digital filters in quadrature mirror filter banks for nuclear magnetic tomography 核磁层析成像用正交镜像滤波器组中的四重数字滤波器
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412977
E. Gescheidtová, Z. Smékal, R. Kuhasek, K. Bartusek
{"title":"Equaripple digital filters in quadrature mirror filter banks for nuclear magnetic tomography","authors":"E. Gescheidtová, Z. Smékal, R. Kuhasek, K. Bartusek","doi":"10.1109/APCCAS.2004.1412977","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412977","url":null,"abstract":"The wavelet transform represents a very favourite tool for removing noise 6om signal on many areas of digital signal processing. A problem consists in that selected wavelet functions are mostly used that in advance defme the impulse response of quadrature minor filters (QMF) of the type of lowpass and highpass filters in a bank of filters. The paper deals with the design of QMF bank using standard design algorithms for digital filters. The Remez algorithm is used here as an example of the design of a bank of partial digital filters.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131064649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A realization of simple current-mode cmos based true RMS-to-DC converter 一种基于cmos的简单电流型真rms - dc变换器的实现
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412983
K. Kaewdang, K. Kumwachara, W. Surakampontorn
{"title":"A realization of simple current-mode cmos based true RMS-to-DC converter","authors":"K. Kaewdang, K. Kumwachara, W. Surakampontorn","doi":"10.1109/APCCAS.2004.1412983","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412983","url":null,"abstract":"A simple circuit technique for the realization of an integrable current-mode CMOS true rms-to-dc converter is proposed. The realization scheme is based on the implicit computation method by makes use of the characteristic of a CMOS squaring circuit. Since the bias current of the circuit is provided by the I,,, the conversion circuit consumes very low power. The performance of the circuit is studied through spectre in Cadence simulation results and experimental results.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132572442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A simplification of the Log-MAP algorithm for turbo decoding turbo译码中Log-MAP算法的简化
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1413065
Lou Xi-zhong, Mao Zhi-gang, Ye Yi-zheng, Chen Yan-Min
{"title":"A simplification of the Log-MAP algorithm for turbo decoding","authors":"Lou Xi-zhong, Mao Zhi-gang, Ye Yi-zheng, Chen Yan-Min","doi":"10.1109/APCCAS.2004.1413065","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1413065","url":null,"abstract":"The Log-MAP algorithm and its modifications were proposed to simplify the VLSI implementation of turbo decoding. This work presents a new way to simplify the Log-MAP algorithm, called Shift-Log-MAP as it takes place of log and exp operation with shift. The correction term in the Log-MAP algorithm was transformed to linear function by use of Taylor equation at the slope of 1/2, 1/4, etc. It allows for efficient ASIC implementation and almost has the same performance as the Log-MAP algorithm.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131618301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Filter design with voltage conveyors 带电压输送机的过滤器设计
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412956
V. Novotny, V. Zeman
{"title":"Filter design with voltage conveyors","authors":"V. Novotny, V. Zeman","doi":"10.1109/APCCAS.2004.1412956","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412956","url":null,"abstract":"This work deals with the procedure of filter design using modern active circuit elements called voltage conveyors. Like in the case of current conveyors, various kinds of voltage conveyors can be designed and used for frequency filter synthesis. As the voltage conveyors have not been manufactured in the form of real electronic devices yet, the paper shows how to construct the design network structures using the available electronic device AD844. Results of the simulations of ideal filter structures and of using the AD844 are presented.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133859252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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