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Modification of context-based arithmetic coding for SPIHT 基于上下文的SPIHT算法编码的改进
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412992
Yung-Chiang Wei, J. Yang, Yi Jiang
{"title":"Modification of context-based arithmetic coding for SPIHT","authors":"Yung-Chiang Wei, J. Yang, Yi Jiang","doi":"10.1109/APCCAS.2004.1412992","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412992","url":null,"abstract":"In this paper, we propose an efficient arithmetic-coding model adapted to the SPIHT algorithm to improve its coding efficiency. With the data dependency and the relationship implied by the SPIHT tree structure, the compression performance of the arithmetic coding for the SPIHT data is improved due to the re-defmed probability model. With this modification, we exploit the parent-child and neighborhood relationships contributed by SPIHT to overcome the spatial redundancy.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116745421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Improved rate control via rate-quantization modeling with kalman filter 通过卡尔曼滤波的速率量化建模改进了速率控制
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1413087
Din-Yuen Chan, Shou-Jen Lin, Chung-Wei Lin
{"title":"Improved rate control via rate-quantization modeling with kalman filter","authors":"Din-Yuen Chan, Shou-Jen Lin, Chung-Wei Lin","doi":"10.1109/APCCAS.2004.1413087","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1413087","url":null,"abstract":"In this paper, we propose a rate control framework for H.263+ using an adaptive rate-quantization (R-Q) model. A characteristic rate function parameterized by a specified quantization parameter can be approximately a linear function of macroblock (MB) activity. During encoding, Kalman filter simultaneously refines the slopes of R-Q characteristic line to trace the change of R-Q relation between two successive clustered MBs (COBS), and the quantization parameters of MBs located in the same COB can be determined based on the latest refined R-Q model. For satisfying real-time demands, the proposed scheme employs a fast method of progressive MB mergence to determine the range of a COB. In the experiments, our framework can obtain higher objective and perceptual qualities over TMNB module. Keyword: H.263+, Rate-Quantization Model, Kalman filter.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128264365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Zero-skew-clock algorithms for high performance system on a chip 芯片上高性能系统的零倾斜时钟算法
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412719
Y. Lai, Yung-Chuan Jiang, Cheng-Hsiung Tsai
{"title":"Zero-skew-clock algorithms for high performance system on a chip","authors":"Y. Lai, Yung-Chuan Jiang, Cheng-Hsiung Tsai","doi":"10.1109/APCCAS.2004.1412719","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412719","url":null,"abstract":"The high performance circuit design has become an essential trend for system-on-a-chip (SoC). Hence, physical design automation is getting more and more complex due to parasitic effects, especially wire delay. We propose a new flexible clock distribution network design to approach solving the clock skew problem and supporting \"plug-and-play\" in SoC integrated overall SoC operation. The algorithm based on clock skew without changing interconnect signal and it can be easily implemented for SoC design flow. The design turn around times can be greatly reduced.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129282730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new current mirror memory cell to improve the power efficiency of CMOS current mode analog circuits 一种新型电流镜像存储单元，可提高CMOS电流模模拟电路的功率效率
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1413062
C. Chan, C. Chan, C. Choy, K. Pun
{"title":"A new current mirror memory cell to improve the power efficiency of CMOS current mode analog circuits","authors":"C. Chan, C. Chan, C. Choy, K. Pun","doi":"10.1109/APCCAS.2004.1413062","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1413062","url":null,"abstract":"This work presents a new technique to improve the power efficiency of CMOS current mode analog circuits. Instead of using the first generation (FG) current memory cells as the major building block for CMOS current mode analog circuit design, we propose a new current mirror memory cell (CMMC). We present our argument by detailed analysis and simulation results to back up our claims. Two delay cells are designed using the FG current memory cell and CMMC. Simulation results show that our approach saves 38.46% of power while achieving similar performance compared with the first generation current memory cells.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130279204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design and simulation of a baseband transceiver for IEEE 802.16a OFDM-mode subscriber stations IEEE 802.16a ofdm模式用户站基带收发器的设计与仿真
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412973
Sang-Jung Yang, Yi Lei, T. Chiueh
{"title":"Design and simulation of a baseband transceiver for IEEE 802.16a OFDM-mode subscriber stations","authors":"Sang-Jung Yang, Yi Lei, T. Chiueh","doi":"10.1109/APCCAS.2004.1412973","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412973","url":null,"abstract":"In this paper, we propose a subscriber station (SS) physical layer (PHY) inner transceiver architecture for IEEE 802.16a OFDM mode. Algorithms for symbol boundary detection, carrier frequency offset (CFO), timing offset (TO) and frequency-domain equalization (FEQ) as well as channel interpolation are embedded in this receiver. Simulation results show that the proposed architecture can fulfill the bit-error-rate (BER) requirements under most situations.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123955055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A multithreaded HDL simulator for deep submicron SoC designs 用于深亚微米SoC设计的多线程HDL模拟器
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412695
T. Chan
{"title":"A multithreaded HDL simulator for deep submicron SoC designs","authors":"T. Chan","doi":"10.1109/APCCAS.2004.1412695","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412695","url":null,"abstract":"This work describes a multithreaded, 64-bit, HDL (hardware description language) simulator, V2Sim/spl trade/, which can significantly accelerate the design verification of advanced deep submicron system-on-chip (SoC) circuits by 10/spl times/ or more on any commercial symmetrical multiprocessing (SMP) computers. This work presents the patented, multithreaded simulation algorithm used by V2Sim/spl trade/, and benchmark results of V2Sim/spl trade/ will be depicted to demonstrate the effectiveness of the state-of-the-art algorithm.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121272836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An alternative scheme of redundant binary multiplier 冗余二进制乘法器的一种备选方案
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412684
Chip-Hong Chang, Yajuan He, J. Gu
{"title":"An alternative scheme of redundant binary multiplier","authors":"Chip-Hong Chang, Yajuan He, J. Gu","doi":"10.1109/APCCAS.2004.1412684","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412684","url":null,"abstract":"This work addresses the feasibility of re-engineering the multiplier architecture that is based on a new redundant number representation called the non-carry-propagation (NCP) format to avoid carry propagation. The preliminary theoretical assessments and simulation result show that this multiplier possesses certain revelatory features that make it a potential alternative approach to conventional redundant binary multiplier. The characteristics of NCP number and the structure of NCP adders array are analyzed. A new reverse converter was also proposed to simplify the converter circuit that converts the final redundant binary number into the corresponding 2's complement number. A recommended gate-level implementation of the multiplier based on this new architecture is also presented.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114776533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A chaos-based fully digital 120 MHz pseudo random number generator 基于混沌的全数字120 MHz伪随机数发生器
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412769
Hsing-Tsung Yang, Jing-Reng Huang, Tsin-Yuan Chang
{"title":"A chaos-based fully digital 120 MHz pseudo random number generator","authors":"Hsing-Tsung Yang, Jing-Reng Huang, Tsin-Yuan Chang","doi":"10.1109/APCCAS.2004.1412769","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412769","url":null,"abstract":"A chaos-based pseudo random number generator (PRNG) is implemented in a fully digital circuit with 120 MHz operation clock frequency. The chaotic equation called logistic equation is applied to the system model of PRNG. Noise can be injected to disturb the iterations with dead operation detected. The random quality of the chaos-based model is measured by the Sp. 800-22 random test package. The chaos-based PRNG has been designed and run in the UMC 1P6M 0.18/spl mu/m CMOS process with area of 944 /spl mu/m /spl times/ 813 /spl mu/m.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114873885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Power aware design of an 8-bit pipelining asynchronous ANT-based CLA using data transition detection 基于数据转换检测的8位流水线异步ant CLA的功耗感知设计
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412683
Chua-Chin Wang, Ching-Li Lee, P. Liu
{"title":"Power aware design of an 8-bit pipelining asynchronous ANT-based CLA using data transition detection","authors":"Chua-Chin Wang, Ching-Li Lee, P. Liu","doi":"10.1109/APCCAS.2004.1412683","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412683","url":null,"abstract":"A high speed and low-power 8-bit carry-lookahead adder (CLA) using two-phase all-N-transistor (ANT) blocks which are arranged in a PLA design style with power-aware pipelining is presented. The pull-up charging and pull-down discharging of the transistor arrays of the PLA are accelerated by inserting two feedback MOS transistors between the evaluation NMOS blocks and the outputs. The addition of two 8-bit binary numbers is executed in 2 cycles. The proposed power-aware pipelining design methodology using a simple data transition detection circuit takes advantage of shutting down the processing stages with identical inputs in two consecutive operations. Not only is it proved to be also suitable for long adders, the dynamic power consumption is drastically reduced by more than 50% at every process corner.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124463748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A binary tree architecture for application specific network on chip (ASNOC) design 二叉树结构的应用特定的网络芯片(ASNOC)设计
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1413019
Y. Jeang, W. Huang, W. Fang
{"title":"A binary tree architecture for application specific network on chip (ASNOC) design","authors":"Y. Jeang, W. Huang, W. Fang","doi":"10.1109/APCCAS.2004.1413019","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1413019","url":null,"abstract":"A mix-mode network on-chip (NOC) interconnection architecture is proposed In this work. The proposed architecture makes use of a globally asynchronous communication network and a locally synchronous bus. Firstly, a local bus is given for a group of cores so that all communications within this local bus are exclusive in time. In order to represent the ratio of communications of this local bus, an user has to provide a communication ratio (CR) of each pair of local bus groups. After that, the two local buses with the highest CR are grouped to be the first switching point for the globally asynchronous network. Then, one can regard the two groups using a switching point as a new group. The new CR hence can be determined from the new and each other local bus group. Similar process is performed to form the next switching point. Finally, a binary tree (BT) is built by setting each internal tree node a switching point while each leaf a local bus. In addition, the switching circuit cost can be decreased while the performance is increased. The simulation results show that the proposed architecture of NOC is better than the general purposed SPIN architecture.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126203136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
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