2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems最新文献_第4页

Flip-Flop Hardening and Selection for Soft Error and Delay Fault Resilience 软错误和延迟故障恢复的触发器强化和选择

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.50

Mingjing Chen, A. Orailoglu

{"title":"Flip-Flop Hardening and Selection for Soft Error and Delay Fault Resilience","authors":"Mingjing Chen, A. Orailoglu","doi":"10.1109/DFT.2009.50","DOIUrl":"https://doi.org/10.1109/DFT.2009.50","url":null,"abstract":"The traditional test model of go/no-go testing being questioned by increasing delay fault manifestations has become even further challenged as a result of unpredictable soft errors. Consequent probabilistic fault manifestations shift the focus to fault resilience mechanisms and tradeoffs of false alarms vs. escapes. Fault manifestation at flip-flops necessitates solutions that rely on their hardening, possibly imposing inordinate cost as flip-flops constitute a significant fraction of current designs. A two-pronged approach for resolving this challenge is necessitated, consisting of frugal flip-flop designs, capable of withstanding such faults, and an economic rationalization model to enable a prioritized flip-flop selection within an overall design budget. In this paper, we propose a hardened flip-flop that increases circuit tolerance to soft errors and delay faults simultaneously and the associated selective hardening scheme guided by a unified quality evaluation framework. The proposed flip-flop supersedes previous research efforts and simulation results show that the outlined framework delivers yield recovery and FIT reduction at a minimized hardware cost.","PeriodicalId":405651,"journal":{"name":"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131460352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Reduced Precision Checking for a Floating Point Adder 降低浮点加法器的精度检查

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.22

Patrick J. Eibl, Andrew D. Cook, Daniel J. Sorin

引用次数: 17

Burst Error Detection Hybrid ARQ with Crosstalk-Delay Reduction for Reliable On-chip Interconnects 具有串扰-延迟降低的突发错误检测混合ARQ用于可靠的片上互连

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.45

Bo Fu, P. Ampadu

引用次数: 21

A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS 一种用于路线图末端CMOS的容错和性能可调门架构

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.65

A. Singh

{"title":"A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS","authors":"A. Singh","doi":"10.1109/DFT.2009.65","DOIUrl":"https://doi.org/10.1109/DFT.2009.65","url":null,"abstract":"In addition to high defect rates, end-of-roadmap CMOS at sub-10 nm gate lengths is also expected to display significant random variability in individual device performance. This will lead to unique and varied slow paths (statistical performance outliers) in individual ICs, severely limiting achievable clock rates. While it is widely accepted that to ensure viable manufacturing yield and reliable field operation, future circuits will need to be equipped with significant defecttolerance capabilities, it is less commonly recognized that continued performance gains from scaling in the face of extreme parameter variations will also require a post manufacture performance tuning capability capable of speeding up the statistical slow paths on individual ICs that limit clock rates. In this paper, we show how a recently proposed defect-tolerant CMOS logic gate architecture can efficiently achieve both these goals. Our basic design exploits the inherent functional redundancy in static CMOS for defect tolerance; the CMOS logic gate is reconfigured to a pseudo-NMOS-like gate in the presence of a defect by using an appropriately sized single pull up or pull down transistor to replace the defective pull-up or pull down network. Thus the resulting defect-tolerant gate architecture can tolerate defects in either the pull-up or pull-down network and incurs only a modest area overhead. Multiple defects across the logic gates in a large CMOS design can also be tolerated. Importantly, these redundant pull up or pull down transistors can also be strategically turned on for performance tuning, speeding up a slow critical transition through a gate at the possible expense of a small slow down in the opposite transition. Results evaluating the effectiveness of the new defect tolerance and performance tuning technique are presented.","PeriodicalId":405651,"journal":{"name":"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130402796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Improving the Detectability of Resistive Open Faults in Scan Cells 提高扫描单元中电阻性开路故障的可检出性

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.30

Fan Yang, S. Chakravarty, Narendra Devta-Prasanna, S. Reddy, I. Pomeranz

引用次数: 15

Dreams, Plans, and Journey of Reaching Perfect Predictability and Reliability in ASICs 实现asic完美可预测性和可靠性的梦想、计划和历程

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.63

N. Sherwani

引用次数: 0

A Sensor to Detect Normal or Reverse Temperature Dependence in Nanoscale CMOS Circuits 一种检测纳米级CMOS电路中正常或反向温度依赖性的传感器

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.47

D. Wolpert, P. Ampadu

引用次数: 20

Improving Memory Repair by Selective Row Partitioning 通过选择行分区改善内存修复

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.20

M. T. Rab, A. A. Bawa, N. Touba

{"title":"Improving Memory Repair by Selective Row Partitioning","authors":"M. T. Rab, A. A. Bawa, N. Touba","doi":"10.1109/DFT.2009.20","DOIUrl":"https://doi.org/10.1109/DFT.2009.20","url":null,"abstract":"A new methodology for improving memory repair is presented which can be applied in either manufacture time repair or built-in self-repair (BISR) scenarios. In traditional memory repair, one spare column can only replace one column containing a defective cell. However, the proposed method allows a single spare column to be used to repair multiple defective cells in multiple columns. This is done by selectively decoding the row address bits when generating the control signals for the column MUXes. This logically segments the spare column allowing it to replace different columns in different partitions of the row address space. The hardware is the same for all chips, but fuses are used to customize the row decoding circuitry on a chip-by-chip basis. An algorithm is described for choosing which row address bits to decode given the defect map for a particular chip. This additional degree of freedom allows customization based on the defect map of a chip and increases the effectiveness of the proposed scheme in comparison to traditional memory repair. Experimental results show that, when compared with traditional schemes of similar complexity, the proposed scheme achieves a higher probability of repairing defects.","PeriodicalId":405651,"journal":{"name":"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131913680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Fault-Tolerant Routing Algorithm for Network on Chip without Virtual Channels 无虚拟通道的片上网络容错路由算法

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.41

Y. Fukushima, Masaru Fukushi, S. Horiguchi

{"title":"Fault-Tolerant Routing Algorithm for Network on Chip without Virtual Channels","authors":"Y. Fukushima, Masaru Fukushi, S. Horiguchi","doi":"10.1109/DFT.2009.41","DOIUrl":"https://doi.org/10.1109/DFT.2009.41","url":null,"abstract":"Constructing 2D mesh topology network on chips (NoCs) without using virtual channels becomes attractive approach to building future massive multi-core computer systems because of its large amount of bandwidths, less design complexity, and less space consumption of routers. Dead lock problem on NoC is critical because it makes data transmission between nodes unreachable, and inevitable failures in hardware make mesh topology irregular. Although several fault-tolerant techniques are available, deadlock-free routing control algorithm for irregular mesh topology is promising approach to utilize large amount of bandwidths of NoC. The main drawback of available routing control algorithms is that many healthy nodes are deactivated to guarantee deadlock-freeness, and a number of deactivated nodes lead to traffic congestion. In this paper, we propose new fault-tolerant routing algorithm on 2D mesh topology NoC constructed without using virtual channels. The proposed algorithm is fully analyzed its dead lock-freeness, and the experimental result shows that the proposed algorithm can achieve both less number of deactivated nodes and higher throughput.","PeriodicalId":405651,"journal":{"name":"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131279351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 41

A Reconfigurable ADC Circuit with Online-Testing Capability and Enhanced Fault Tolerance 具有在线测试能力和增强容错能力的可重构ADC电路

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.31

Yueran Gao, Haibo Wang

引用次数: 4