2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems最新文献_第3页

System Level Testing via TLM 2.0 Debug Transport Interface 通过TLM 2.0调试传输接口进行系统级测试

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.46

S. Carlo, N. Hatami, P. Prinetto, A. Savino

引用次数: 2

Resilience Challenges for Exascale Systems 百亿亿级系统的弹性挑战

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.52

N. Jouppi

引用次数: 1

Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR) 基于分布式R-fold模块冗余的大缺陷密度下纳米电子系统可靠性优化

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.54

M. Stanisavljevic, A. Schmid, Y. Leblebici

引用次数: 12

Thermal Driven Test Access Routing in Hyper-interconnected Three-Dimensional System-on-Chip 超互连三维片上系统的热驱动测试访问路由

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.42

Unni Chandran, Dan Zhao

引用次数: 18

SNR-Aware Error Detection for Low-Power Discrete Wavelet Lifting Transform in JPEG 2000 JPEG 2000中低功耗离散小波提升变换的信噪比感知误差检测

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.17

Shih-Hsin Hu, Tung-Yeh Wu, J. Abraham

引用次数: 1

Generating Diverse Test Sets for Multiple Fault Detections Based on Fault Cone Partitioning 基于故障锥划分的多故障检测多测试集生成

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.24

Stelios N. Neophytou, M. Michael, Kyriakos Christou

{"title":"Generating Diverse Test Sets for Multiple Fault Detections Based on Fault Cone Partitioning","authors":"Stelios N. Neophytou, M. Michael, Kyriakos Christou","doi":"10.1109/DFT.2009.24","DOIUrl":"https://doi.org/10.1109/DFT.2009.24","url":null,"abstract":"Testing modeled faults multiple times has been shown to increase the likelihood of a test set to detect non-modeled faults, either static or dynamic, when compared to a single detect test set. Test sets that guarantee detecting every modeled fault with at least n different tests are known as n-detect test sets. Moreover, recent investigations examine how different the various tests for a fault should be, in order to further increase their ability in detecting defects. This work proposes a new test generation methodology for multiple-detect (including n-detect) test sets that increases their diversity in terms of the various fault propagation paths excited by the different tests. Specifically, the various tests per modeled fault are guaranteed to propagate the fault effect via different propagation paths. The proposed method can be applied to any linear, to the circuit size, static or dynamic fault model for multiple fault detections, such as the stuck-at or transition delay fault models, and avoids any path or path segment enumeration. Experimental results show increased numbers of propagation paths and non-modeled fault coverages when compared to traditional n-detect test sets.","PeriodicalId":405651,"journal":{"name":"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122185002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A Fault Analysis and Classifier Framework for Reliability-Aware SRAM-Based FPGA Systems 基于sram的可靠性感知FPGA系统故障分析与分类器框架

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.10

C. Bolchini, F. Castro, A. Miele

引用次数: 13

A Study of Side-Channel Effects in Reliability-Enhancing Techniques 可靠性增强技术中的边信道效应研究

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.32

Jianwei Dai, Lei Wang

引用次数: 12

Coded DNA Self-Assembly for Error Detection/Location 错误检测/定位的编码DNA自组装

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.13

Z. M. Arani, M. Hashempour, F. Lombardi

引用次数: 2

Defect-Tolerant Logic Mapping on Nanoscale Crossbar Architectures and Yield Analysis 纳米尺度横杆结构的容错逻辑映射及良率分析

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.16

Yehua Su, Wenjing Rao

{"title":"Defect-Tolerant Logic Mapping on Nanoscale Crossbar Architectures and Yield Analysis","authors":"Yehua Su, Wenjing Rao","doi":"10.1109/DFT.2009.16","DOIUrl":"https://doi.org/10.1109/DFT.2009.16","url":null,"abstract":"Crossbar architectures are promising in the emerging nanoelectronic environment. However, fabrication processes for nano-scale circuits introduce numerous defects. Logic mapping on these defective nanofabrics thus emerges as a fundamental challenge. We establish a mathematical model for the logic mapping problem, followed by a probabilistic analysis to gain yield information. Since the most challenging part of the problem is the exponential runtime in searching for a solution, we examine the practical perspective of yield where a runtime limit is imposed. Yield improvement can be achieved through one of two ways: adding hardware redundancy by increasing crossbar size or allowing longer runtime. It turns out that correlations in the mapping solution space play an essential role on the complexity of the problem. Therefore, developing effective mechanisms to improve yield requires insights and analysis on correlations in the solution space. The analysis provided in this paper reveals the following points. Even though yield can always be improved through increasing crossbar size, the improvement gained by increasing crossbar size has a theoretical upperbound when a runtime limit is imposed. Consequently, there exists an optimal size for a crossbar to improve yield effectively within a runtime limit. Last but not least, for large-sized logic functions, longer runtime can be invested to improve yield significantly.","PeriodicalId":405651,"journal":{"name":"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125319895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 23