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SOI CMOS technology for quantum information processing 用于量子信息处理的SOI CMOS技术
2017 IEEE International Conference on IC Design and Technology (ICICDT) Pub Date : 2017-05-01 DOI: 10.1109/ICICDT.2017.7993523
L. Hutin, B. Bertrand, R. Maurand, M. Urdampilleta, B. Jadot, H. Bohuslavskyi, L. Bourdet, Y. Niquet, X. Jehl, S. Barraud, C. Bauerle, T. Meunier, M. Sanquer, S. D. Franceschi, M. Vinet
{"title":"SOI CMOS technology for quantum information processing","authors":"L. Hutin, B. Bertrand, R. Maurand, M. Urdampilleta, B. Jadot, H. Bohuslavskyi, L. Bourdet, Y. Niquet, X. Jehl, S. Barraud, C. Bauerle, T. Meunier, M. Sanquer, S. D. Franceschi, M. Vinet","doi":"10.1109/ICICDT.2017.7993523","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993523","url":null,"abstract":"We present some recent progress towards the implementation of semiconductor spin quantum bits derived from a Si CMOS technology platform. Our approach consists in developing a foundry-compatible embodiment of the basic building block of quantum information, with a strong potential for large scale co-integration of a quantum core with its mandatory classical control and readout electronics. After introducing various qubit manipulation, coupling and readout schemes, we discuss some prospects for scalability, and in particular some potential advantages of the FDSOI technology.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134171860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design considerations for optimization of pull-in stability margin in electrostatic N/MEM relays 静电N/MEM继电器拉入稳定裕度优化的设计考虑
2017 IEEE International Conference on IC Design and Technology (ICICDT) Pub Date : 2017-05-01 DOI: 10.1109/ICICDT.2017.7993522
G. Usai, L. Hutin, J. L. Muñoz-Gamarra, T. Ernst, M. Vinet, P. Feng
{"title":"Design considerations for optimization of pull-in stability margin in electrostatic N/MEM relays","authors":"G. Usai, L. Hutin, J. L. Muñoz-Gamarra, T. Ernst, M. Vinet, P. Feng","doi":"10.1109/ICICDT.2017.7993522","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993522","url":null,"abstract":"This study aims at providing guidelines for designing electrostatically-actuated micro/nanoelectromechanical relays with a broad operating margin around the supply voltage VDD. Whereas it is tempting to focus mainly on minimizing the first pull-in voltage (Vpi) in order to enable a low VDD, special attention should be paid to the so-called catastrophic pull-in (Vcpi), which corresponds to the movable electrode collapsing onto the actuating electrode for a sufficiently large overdrive. Based on analytical and finite element analysis (FEA) modeling, we study the dependence of a functionality margin defined as (Vcpi-Vpi) versus the size and position of the actuating electrode with respect to the movable structure.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127777139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electrons, phonons, and unconventional applications of 2D materials 电子、声子和二维材料的非常规应用
2017 IEEE International Conference on IC Design and Technology (ICICDT) Pub Date : 2017-05-01 DOI: 10.1109/ICICDT.2017.7993519
E. Pop, E. Yalon, M. Muñoz-Rojo, M. Mleczko, C. English, Ning Wang, K. Smithe, S. Suryavanshi, I. Datye, C. McClellan, A. Gabourie
{"title":"Electrons, phonons, and unconventional applications of 2D materials","authors":"E. Pop, E. Yalon, M. Muñoz-Rojo, M. Mleczko, C. English, Ning Wang, K. Smithe, S. Suryavanshi, I. Datye, C. McClellan, A. Gabourie","doi":"10.1109/ICICDT.2017.7993519","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993519","url":null,"abstract":"This invited talk will present recent highlights from our research on two-dimensional (2D) materials including graphene, boron nitride (h-BN), and transition metal dichalcogenides (TMDs). The results span from fundamental measurements and simulations, to device- and several unusual system-oriented applications which take advantage of unique 2D material properties. Basic electrical, thermal, and thermoelectric properties of 2D materials will also be discussed.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"413 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124420318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power consumption estimation using VNOC2.0 simulator for a fuzzy-logic based low power Network-on-Chip 基于模糊逻辑的低功耗片上网络vno2.0仿真器的功耗估计
2017 IEEE International Conference on IC Design and Technology (ICICDT) Pub Date : 2017-05-01 DOI: 10.1109/ICICDT.2017.7993515
Hai-Phong Phan, Xuan-Tu Tran, T. Yoneda
{"title":"Power consumption estimation using VNOC2.0 simulator for a fuzzy-logic based low power Network-on-Chip","authors":"Hai-Phong Phan, Xuan-Tu Tran, T. Yoneda","doi":"10.1109/ICICDT.2017.7993515","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993515","url":null,"abstract":"Dynamic Voltage and Frequency Scaling (DVFS) has been known as an efficient technique to reduce the power consumption of a Network-on-Chip (NoC). An important question in DVFS is how to change the voltage and frequency adaptable to the required performance of the system at run-time while reducing the power consumption as much as possible. Another problem is how a tool could quickly and efficiently validate or reject a NoC architecture employing DVFS. By integrating the Orion 2 power model, VNOC 2.0 simulator can be used as either a NoC simulation tool or a platform for implementing and investigating DVFS ideas. In this paper, we focus on developing a new solution for NoC architectures to save energy using fuzzy-logic algorithms. A controller is designed to predict the change of traffic load based on the fuzzy logic algorithm, then adjusts the voltage and frequency correspondingly to minimize the power consumption while keeping the performance of the whole system. An estimation of power consumption has been done by using VNOC 2.0 simulator. The simulation results show that our model can save up to 46% the power consumption of a 8×8 NoC.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124433764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
FD-SOI material enabling CMOS technology disruption from 65nm to 12nm and beyond FD-SOI材料使CMOS技术从65nm突破到12nm及以上
2017 IEEE International Conference on IC Design and Technology (ICICDT) Pub Date : 2017-05-01 DOI: 10.1109/ICICDT.2017.7993499
W. Schwarzenbach, M. Sellier, Bich-Yen Nguyen, C. Girard, C. Maleville
{"title":"FD-SOI material enabling CMOS technology disruption from 65nm to 12nm and beyond","authors":"W. Schwarzenbach, M. Sellier, Bich-Yen Nguyen, C. Girard, C. Maleville","doi":"10.1109/ICICDT.2017.7993499","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993499","url":null,"abstract":"Multiples technology nodes in production are now based on FD-SOI thin film substrates. The development of these substrates has required several technical innovations (SmartCut process adaptation, new metrology introduction), which are discussed in this paper.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"414 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133910576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Innovative and 3D stacking Micro Electro Mechanical Systems (I-MEMS) for power saving 创新和3D堆叠微机电系统(I-MEMS)，节省电力
2017 IEEE International Conference on IC Design and Technology (ICICDT) Pub Date : 2017-05-01 DOI: 10.1109/ICICDT.2017.7993518
K. Mori, Giang Dao, Ziep Tran, Michael Ramon, J. Woo, Peng Lu
{"title":"Innovative and 3D stacking Micro Electro Mechanical Systems (I-MEMS) for power saving","authors":"K. Mori, Giang Dao, Ziep Tran, Michael Ramon, J. Woo, Peng Lu","doi":"10.1109/ICICDT.2017.7993518","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993518","url":null,"abstract":"The Innovative Micro Electro Mechanical Systems (I-MEMS) device was developed to reduce the power consumption of next-generation electronic devices. I-MEMS devices eliminate standby power when used as a power gating device. In logic circuit applications, I-MEMS devices provide for extremely low power consumption and remain robust during high temperature operation. I-MEMS devices are very reliable and can operate at current CMOS digital voltage (1V). This paper will review current MOSFET and MEMS technologies, analyze problems in conventional MEMS, and provide solutions for these problems.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132611773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Yield and energy tradeoffs of an NVLatch design using radial sampling 采用径向采样的NVLatch设计的产量和能量权衡
2017 IEEE International Conference on IC Design and Technology (ICICDT) Pub Date : 2017-05-01 DOI: 10.1109/ICICDT.2017.7993511
Adam Issa, R. Kanj, A. Chehab, R. Joshi
{"title":"Yield and energy tradeoffs of an NVLatch design using radial sampling","authors":"Adam Issa, R. Kanj, A. Chehab, R. Joshi","doi":"10.1109/ICICDT.2017.7993511","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993511","url":null,"abstract":"Nonvolatile latches are increasingly popular with the advent of IoT design. We study the yield energy tradeoff of the backup mechanism of an STT-MTJ based nonvolatile latch. For the yield analysis, we rely on Hicks and Wheeling methodology for multi-cone radial sampling for the purpose of rare fail estimation. Yield is shown to be delimited by the Parallel-to-AntiParallel magnetic angle transitions. To accommodate for the slower cells, we note an increase in the average energy requirements for the backup mechanism. Simulations indicate an increase of 10%–40% for the average energy requirements to achieve an ideal yield requirement close to 99% for different number of components.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130849570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Advances of the development of a ferroelectric field-effect transistor on Ge(001) Ge(001)基铁电场效应晶体管的研制进展
2017 IEEE International Conference on IC Design and Technology (ICICDT) Pub Date : 2017-05-01 DOI: 10.1109/ICICDT.2017.7993524
P. Ponath, A. Posadas, Yuan Ren, Xiaoyu Wu, K. Lai, A. Demkov, Michael Schmidt, R. Duffy, P. Hurley, Jian Wang, C. Young, R. Vasudevan, M. Okatan, S. Jesse, Sergei V. Kalinin
{"title":"Advances of the development of a ferroelectric field-effect transistor on Ge(001)","authors":"P. Ponath, A. Posadas, Yuan Ren, Xiaoyu Wu, K. Lai, A. Demkov, Michael Schmidt, R. Duffy, P. Hurley, Jian Wang, C. Young, R. Vasudevan, M. Okatan, S. Jesse, Sergei V. Kalinin","doi":"10.1109/ICICDT.2017.7993524","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993524","url":null,"abstract":"Here we report the recent advances towards the ferroelectric field-effect on Ge(001). We will demonstrate carrier density modulation in the underlying Ge(001) substrate by switching the ferroelectric polarization in the epitaxial c-axis-oriented BaTiO3 on Ge. Recent results of patterning BaTiO3 for device applications and electrical properties of Pt/BTO/Ge heterostructures will be addressed.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123669268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 910nW delta sigma modulator using 65nm SOTB technology for mixed signal IC of IoT applications 采用65nm SOTB技术的910nW δ σ调制器，用于物联网应用的混合信号IC
2017 IEEE International Conference on IC Design and Technology (ICICDT) Pub Date : 2017-05-01 DOI: 10.1109/ICICDT.2017.7993514
K. Ishibashi, Junya Kikuchi, N. Sugii
{"title":"A 910nW delta sigma modulator using 65nm SOTB technology for mixed signal IC of IoT applications","authors":"K. Ishibashi, Junya Kikuchi, N. Sugii","doi":"10.1109/ICICDT.2017.7993514","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993514","url":null,"abstract":"A 910nW 46fJ/conv 0.036mm2 delta sigma modulator is demonstrated. The chip was fabricated using 65nm SOTB (Silicon on Thin Buried oxide) technology, in which 13.4pJ/cycle 0.14uA Sleep Current CPU with 15nA VBB generator was obtained, resulting in achieving ultra-low power mixed signal IC for IoT applications.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"20 25-26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123595236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Process variation aware STT-RAM simulation tool: NVSim-VXs 进程变化感知的STT-RAM仿真工具:nvsim - vx
2017 IEEE International Conference on IC Design and Technology (ICICDT) Pub Date : 1900-01-01 DOI: 10.1109/icicdt.2017.7993508
{"title":"Process variation aware STT-RAM simulation tool: NVSim-VXs","authors":"","doi":"10.1109/icicdt.2017.7993508","DOIUrl":"https://doi.org/10.1109/icicdt.2017.7993508","url":null,"abstract":"Spin-transfer torque random access memory (STT-RAM) recently received significant attentions for its promising characteristics in cache and memory applications. As an early-stage modeling tool, NVSim has been widely adopted for simulations of emerging nonvolatile memory technologies in computer architecture research, including STT-RAM, ReRAM, PCM, etc. In this work, we introduce a new member of NVSim family - NVSim-VXs, which enables statistical simulation of STT-RAM for write performance, errors, and energy consumption. This enhanced model takes into account the impacts of parametric variabilities of CMOS and MTJ devices and the chip operating temperature. It is also calibrated with Monte-Carlo Simulations based on macro-magnetic and SPICE models, covering five technology nodes between 22nm and 90nm. NVSim-VXs strongly supports the fast-growing needs of STT-RAM research on reliability analysis and enhancement, announcing the next important stage of NVSim development.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132166471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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