{"title":"Wideband inductorless CMOS RF front-end for LTE receivers","authors":"Eman Badr, H. Shawkey, Y. Ismail, A. Zekry","doi":"10.1109/ICICDT.2017.7993505","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993505","url":null,"abstract":"This paper presents a new design of inductorless wideband front-end receiver using 130 nm CMOS technology for LTE bands of 0.7 GHz to 3 GHz. The RF front-end receiver consists of the microstrip antenna, self-bias resistive feedback low-noise amplifier, active balun and folded mixer architecture. The miniature antenna provides good matching results for the entire band of interest. Optimization of low-noise amplifier using linearization technique followed by NMOS switches mixer stage are effectively used to achieve maximum gain, low noise figure, and low power consumption. The designed receiver exhibits a maximum gain of 22 dB, maximum noise figure of 7.5 dB, minimum 3rd order intercept point (IIP3) of −9.2 dBm, and DC power consumption of 22 mW at 1.2 V power supply. Using these optimizations, our proposed receiver can be a good candidate for LTE applications.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"202 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123175191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Gilmer, T. Rueckes, L. Cleveland, Darlene Viviani
{"title":"NRAM status and prospects","authors":"D. Gilmer, T. Rueckes, L. Cleveland, Darlene Viviani","doi":"10.1109/ICICDT.2017.7993504","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993504","url":null,"abstract":"Advanced memory technology based on carbon nanotubes (NRAM) has been shown to possess desired properties for implementation in a host of integrated systems due to demonstrated advantages of its operation including high speed (Nanotubes can switch state in picoseconds), high endurance (over a trillion), and low power (with essential zero standby power). The applicable integrated systems have markets that will see compound annual growth rates (CAGR) of over 62% between 2018 and 2023, with an embedded systems CAGR of 115% in 2018 to 2023 [1]. These opportunities for NRAM technology are helping drive the realization of a shift from silicon to a carbon-based memory. NRAM is made up of an interlocking matrix of carbon nanotubes, either touching or slightly separated, leading to low or higher resistance states respectively. The small movement of atoms, as opposed to electrons for traditional memories, renders NRAM with a more robust endurance and high temperature retention/operation which, along with high speed/low power, is expected to blossom in this memory technology to be a disruptive replacement for the current status quo of DRAM (dynamic RAM), SRAM (static RAM), and NAND flash memories.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127488670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fluids energy harvesting system with low cut-in velocity piezoelectric MEMS","authors":"G. E. Biccario, M. Vittorio, S. D'Amico","doi":"10.1109/ICICDT.2017.7993506","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993506","url":null,"abstract":"Energy harvesting from environmental vibrations has established as an effective and green solution for electric energy production. In particular, fluid flows like the wind represent a steady and ubiquitous energy source. Traditional fluids harvesters are based on huge and bulky infrastructures like turbines, with a high environmental impact and a quite high cut-in speed (higher than 3÷4 m/s) for the fluids to be harvested. Transducers based on piezo-electric devices in the micrometric scale have pushed this value down by about one order of magnitude. The development of nanostructured piezo-electric transducers in the submicrometric scale offers a new generation of devices capable of converting the energy of very slow fluids (velocities lower than 1 m/s), like human breath, thanks to their high flexibility. The electronic interface circuit demanded of harvesting the energy from such a transducer is called to sense output signals of hundreds of millivolts with power equal to few microwatts or less. Active architectures must be employed even though they suffer for a start-up phase and the power demand. For building up the circuit supply voltage in few hundreds of milliseconds with the mentioned input power, we propose the employment of two storage devices so that the powering of interface circuit is decoupled from the energy storing. For harvesting all the peaks of the input waveform down to 50 mV, a detector based on current sensing and offset rejection through AC coupling is proposed.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130797367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. H. Bao, S. Sakhare, J. Ryckaert, A. Spessot, D. Verkest, A. Mocuta
{"title":"SRAM designs for 5nm node and beyond: Opportunities and challenges","authors":"T. H. Bao, S. Sakhare, J. Ryckaert, A. Spessot, D. Verkest, A. Mocuta","doi":"10.1109/ICICDT.2017.7993502","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993502","url":null,"abstract":"The rising demand for battery-powered devices is the key driver for continued density scaling and improved power in SoCs. Along with advantages, random VT variation and interconnect RC delay is increased due to the continual scaling of physical dimensions, which seriously degrades SRAM performances, limits VMIN, and makes SRAM less energy efficient. Although FinFET technology can offer a respectable source channel effects (SCEs) and superior VT variation, the competing between channel length (Lg), sidewall spacers, and source/drain (S/D) contacts imposed by contacted gate pitch (CGP) scaling remains unchanged. In this paper, we will present a holistic approach for 6T-SRAM designs using gate-all-around (GAA) transistors, which will firmly address process integrations and circuit aspects arising at the 5nm node. Several read and write assist techniques including wordline (WL) delayed overdrive, VDD collapse and negative bitline (BL) will be exclusively investigated to enable low VMIN and high-performance SRAMs.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126236514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Dadda Multiplier designs using memristors","authors":"Lauren Guckert, E. Swartzlander","doi":"10.1109/ICICDT.2017.7993521","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993521","url":null,"abstract":"Memristors have recently become a leader in future system design due to their unique storage abilities and high density. This work presents an optimized Dadda Multiplier using memristors and IMPLY logic. The design reduces the baseline delay by 30% and complexity by 50% and has fewer than 60% the components of the CMOS design. The design is also pipelined to achieve 3× the throughput of CMOS.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129157060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Layout engineering to suppress hysteresis of negative capacitance FinFET","authors":"Eunah Ko, Jaesung Jo, C. Shin, B. Nguyen","doi":"10.1109/ICICDT.2017.7993498","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993498","url":null,"abstract":"Negative capacitance (NC), which arises from two energy minima of ferroelectric material, is proposed as one of the solutions for the next generation CMOS technology. However, the side-effect (i.e., hysteresis in current-vs.-voltage characteristic) of NC FinFET should be minimized, especially for being adopted as CMOS logic devices. If the capacitance matching between the ferroelectric capacitor and the dielectric capacitor in NC FinFET is satisfied, hysteresis-free and steep switching features can be obtained. In this work, the hysteresis in current-vs.-voltage characteristic is suppressed by lowering the capacitance value of FinFET (i.e., using the layout engineering for FinFET): While the hysteresis of NC FinFET was decreased, the performance degradation was negligible.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116822767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Interfacial transition layer in thermally grown SiO2 film on 4H-SiC","authors":"R. Hasunuma","doi":"10.1109/ICICDT.2017.7993525","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993525","url":null,"abstract":"The uniformity of SiO2 films thermally grown on 4H-SiC was characterized by atomic force microscopic observation of the SiO2 surface after each step-etching with HF solution. It was found that roughness of the emerged SiO2 surface drastically increases near the SiO2/SiC interface, which indicates that the film quality near the interface is not two-dimensionally uniform. The film density profile led to the model that the non-uniformity was generated by segregation of C impurities followed by CO adsorption, and the film uniformity was gradually improved during the subsequent oxidation by shrinkage of open spaces.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123077306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Integrated electrical sensing for high-throughput bioanalytics","authors":"C. Guiducci","doi":"10.1109/ICICDT.2017.7993520","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993520","url":null,"abstract":"Miniaturized and stand-alone assays hold the promise to revolutionize individualized medicine, especially so in the form of liquid biopsy tests and cellular samples manipulation systems, but they currently suffer from various drawbacks, such as the lack of throughput, stability and manufacturability. Our most significant achievements include lab-on-chip/CMOS integration solutions and a novel technology for microfluidic-embedded microsensors that represent unique and highly exploitable technologies. By leveraging multiple collaborations with clinical partners, my lab succeeded in developing innovative analytical solutions in the field of molecular analytics and in the area of single-cell manipulation and characterization on chip.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127098286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Takuya Komawaki, M. Yabuuchi, Ryo Kishida, J. Furuta, Takashi Matsumoto, Kazutoshi Kobayashi
{"title":"Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS","authors":"Takuya Komawaki, M. Yabuuchi, Ryo Kishida, J. Furuta, Takashi Matsumoto, Kazutoshi Kobayashi","doi":"10.1109/ICICDT.2017.7993526","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993526","url":null,"abstract":"As device sizes are downscaled to nanometer, Random Telegraph Noise (RTN) becomes dominant. It is indespensable to accurately estimate the effect of RTN. We propose the RTN simulation method for analog circuits. It is based on the charge trapping model. We replicate the RTN-induced threshold voltage fluctuation to attach a variable DC voltage source to the gate of MOSFET by using Verilog-AMS. We confirm that drain current of MOSFETs temporally fluctuates. The fluctuations of RTN are different for each MOSFET. Our proposed method can be applied to estimate the temporal impact of RTN including multiple transistors. We can successfully replicate RTN-induced frequency fluctuations in 3-stage ring oscillators as similar as the measurement results.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133602529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mohit Kumar Gupta, P. Weckx, S. Cosemans, P. Schuddinck, R. Baert, D. Jang, Y. Sherazi, P. Raghavan, A. Spessot, A. Mocuta, W. Dehaene
{"title":"Dedicated technology threshold voltage tuning for 6T SRAM beyond N7","authors":"Mohit Kumar Gupta, P. Weckx, S. Cosemans, P. Schuddinck, R. Baert, D. Jang, Y. Sherazi, P. Raghavan, A. Spessot, A. Mocuta, W. Dehaene","doi":"10.1109/ICICDT.2017.7993503","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993503","url":null,"abstract":"As scaling continues for FinFET technology nodes, variability in combination with targeted lower supply voltages results in reduced SRAM stability margins. In this paper, threshold voltage tuning from the technological side is used to enable low SRAM Vmin with minimum impact on logic performance. Furthermore, lower overall system energy consumption can be achieved by the lower Vmin. This exercise is crucial for the enablement of future technology nodes where single VTH masks could become a necessity.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133609204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}