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2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)最新文献

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Photoresist developer reclamation technology and system 光刻胶显影剂回收技术及系统
2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203) Pub Date : 2001-10-08 DOI: 10.1109/ISSM.2001.963020
H. Sugawara, Y. Tajima, T. Ohmi
{"title":"Photoresist developer reclamation technology and system","authors":"H. Sugawara, Y. Tajima, T. Ohmi","doi":"10.1109/ISSM.2001.963020","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963020","url":null,"abstract":"A tetramethylammonium hydroxide (TMAH) generally used as photoresist developer for manufacturing LSIs and LCDs is recovered from developer waste (spent developer) using an electrodialysis (ED) method, and purified by ion exchange (IE) technologies. Reclaimed developer features analytically the same purity as commercial fresh one. This reclamation system can achieve a stably high TMAH recovery rate of more than 80%. Furthermore, it has the great advantages of saving operating costs, which amounts to 66.2% (for LSI) and 78.3% (for LCD) total cost reduction compared with conventional no reclamation system in a case study, as well as reducing environmental load.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134576537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Simple tool of analysis for cycle time reduction 简单的分析工具，减少周期时间
2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203) Pub Date : 2001-10-08 DOI: 10.1109/ISSM.2001.962919
T. Sada, R. A. Yuen, M. Ichikawa, M. Yamada, K. Kabata
{"title":"Simple tool of analysis for cycle time reduction","authors":"T. Sada, R. A. Yuen, M. Ichikawa, M. Yamada, K. Kabata","doi":"10.1109/ISSM.2001.962919","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962919","url":null,"abstract":"This paper describes a simple and easy to understand technique of achieving cycle time reduction in a semiconductor fab. The technique uses a spreadsheet that calculates theoretical queue time (based on operations research queuing theory) with consideration to the negative effect of very high priority lots (\"super hot lots\"). The theoretical queue time is compared with actual queue times to identify factory bottlenecks and the best opportunities for cycle time improvement. When this queue time control was introduced, jab cycle time improved 24%.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133525803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Photoresist stripping using novel sulfuric/ozone process 新型硫酸/臭氧法光刻胶剥离
2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203) Pub Date : 2001-10-08 DOI: 10.1109/ISSM.2001.962948
H. Tomita, M. Sato, S. Nadahara, T. Saitoh
{"title":"Photoresist stripping using novel sulfuric/ozone process","authors":"H. Tomita, M. Sato, S. Nadahara, T. Saitoh","doi":"10.1109/ISSM.2001.962948","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962948","url":null,"abstract":"Sulfuric acid (H/sub 2/SO/sub 4/) and ozone (O/sub 3/) mixture process (SOM) with in-situ concentration monitor for O/sub 3/ and peroxyso-di-sulfuric acid (H/sub 2/S/sub 2/O/sub 8/) was developed Ultraviolet spectrometers with 190-200 nm and 254 nm of wavelength were used to detect H/sub 2/S/sub 2/O/sub 8/ and O/sub 3/ dissolved in SOM, respectively. In order to mix H/sub 2/SO/sub 4/ and O/sub 3/ effectively, the O/sub 3/ gas ejectors were jointed to a quartz bath directly. Using SOM process with UV oxidant monitors and O/sub 3/ gas ejectors, heavily dosed resist and dry etched resist could be removed perfectly without dry ashing process.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133441865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Cleaning technique of hot-wall batch type Ru CVD equipment by oxygen gas 热壁间歇式Ru CVD设备氧气清洗技术
2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203) Pub Date : 2001-10-08 DOI: 10.1109/ISSM.2001.962972
D. Choi, D. Nozu, K. Hasebe, T. Shibata, K. Nakao, M. Izuha, H. Akahori, T. Aoyama, K. Eguchi, K. Hieda, T. Arikado, K. Okumura
{"title":"Cleaning technique of hot-wall batch type Ru CVD equipment by oxygen gas","authors":"D. Choi, D. Nozu, K. Hasebe, T. Shibata, K. Nakao, M. Izuha, H. Akahori, T. Aoyama, K. Eguchi, K. Hieda, T. Arikado, K. Okumura","doi":"10.1109/ISSM.2001.962972","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962972","url":null,"abstract":"The gas cleaning of the hot-wall batch type Ru CVD reactor by oxygen was investigated. The cleaning mechanism is considered as follows. Below 800/spl deg/C, Ru film is oxidized and forms RuO/sub 2/ which is not volatile. But above 800/spl deg/C, RuO/sub 2/ film, which is formed at first, is oxidized again to form RuO/sub 4/. Since RuO/sub 4/ is volatile, it evaporates easily. High temperature, low pressure and high oxygen flow rate were required to obtain fast Ru etching rate. With these optimum cleaning conditions by design of experiments (DOE), 30-nm-thick Ru film was removed completely in 20 minutes. We could accomplish this in situ oxygen gas cleaning effectively in short time by using hot-wall batch type Ru CVD equipment, which has high heating and cooling rate characteristics.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123227644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dynamic simulator for WIP analysis in semiconductor manufacturing 半导体制造中在制品分析的动态模拟器
2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203) Pub Date : 2001-10-08 DOI: 10.1109/ISSM.2001.962917
D. Collins, V. Lakshman, L. Collins
{"title":"Dynamic simulator for WIP analysis in semiconductor manufacturing","authors":"D. Collins, V. Lakshman, L. Collins","doi":"10.1109/ISSM.2001.962917","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962917","url":null,"abstract":"We present a FAB Simulator (FS) and Capacity Planner (CP) that permits the operational planner to introduce new product into an existing production mix with confidence as to the customer delivery dates and FAB Capacity This paper describes the implementation of these two dynamic tools in a semiconductor FAB in Arizona. These tools assist the operational planner with the planning of the daily production mix. This FAB produces 100's of different bipolar devices using 36 process flows. The key to success in calculating present and future production goals is real time operational level tracking. Real time tracked data includes data gathered from the Manufacturing Execution System (MES) for each product's work-in-process (WIP), process flow routing, and data gathered from the equipment utilization and emergency maintenance databases. This key information is fed through a GUI linked to the CP which in turn controls the stochastic dynamic simulation model of the FS. These links provide the operational planner with dynamic production data in real time and simulated time for decision-making. The CP and FS are running in parallel and are linked directly with the FAB's MES maintaining current production data.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129380047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Optimization and economic analysis for tool portfolio planning in semiconductor manufacturing 半导体制造中刀具组合规划的优化与经济分析
2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203) Pub Date : 2001-10-08 DOI: 10.1109/ISSM.2001.962908
C.-S. Wu, Y. Chou, J.-Z. Lin
{"title":"Optimization and economic analysis for tool portfolio planning in semiconductor manufacturing","authors":"C.-S. Wu, Y. Chou, J.-Z. Lin","doi":"10.1109/ISSM.2001.962908","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962908","url":null,"abstract":"The tool portfolio of a plant refers to the makeup, in quantity and type, of processing machines in the plant. Portfolio planning is a multi-criteria decision-making task involving trade-offs between investment cost, throughput, cycle time and risk. In this paper, an economic decision model is first presented for optimal configuration of portfolio and to determine optimal factory loading. If plants are closely located or have a twin-fab design, portfolio planning at multiple plants can be integrated to enhance the overall effectiveness of portfolios. A novel methodology for arbitrating capacity backup between multiple plants is described in the second part. Finally, robust configuration of portfolio in a dynamic demand environment is addressed. Industry data have been utilized to run through the developed methodologies.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127183779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Interferometric techniques for dielectric trench etch applications 介电沟槽刻蚀的干涉测量技术
2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203) Pub Date : 2001-10-08 DOI: 10.1109/ISSM.2001.963002
C. Frum, Z. Sui, Hongching Shan
{"title":"Interferometric techniques for dielectric trench etch applications","authors":"C. Frum, Z. Sui, Hongching Shan","doi":"10.1109/ISSM.2001.963002","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963002","url":null,"abstract":"In this paper, we present an in-situ interferometric technique to control the trench depth for etching various type of patterned dielectric films, including silicon oxide, low-k black diamond, and low k SILK materials. We present the data on etching oxide trench wafers with various pattern density on Si substrate, black diamond film on Si, and SILK on Si, using Applied Materials' MERIE dielectric etch chambers. A good correlation between predicted etch depth using interferometric signals and SEM depth data is presented. In addition, the issues of integrating this sensor into a dielectric etch chamber are addressed.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"2162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127468354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low k material optimization 低k材料优化
2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203) Pub Date : 2001-10-08 DOI: 10.1109/ISSM.2001.962949
K. Macwilliams, J. Huang, M. Schulberg, P. van Cleemput
{"title":"Low k material optimization","authors":"K. Macwilliams, J. Huang, M. Schulberg, P. van Cleemput","doi":"10.1109/ISSM.2001.962949","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962949","url":null,"abstract":"A primary challenge in building integrated circuits with geometries of 0.13 /spl mu/m and smaller is the development of materials with low dielectric constants. The properties of the low k films must be compatible with subsequent processing for integration. The present work describes the influence of the starting materials (precursors) and of the deposition process on the electrical and mechanical properties of the low k film.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128917646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Advanced EB-cure process and equipment for low-k dielectric 先进的低钾电介质eb -固化工艺及设备
2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203) Pub Date : 2001-10-08 DOI: 10.1109/ISSM.2001.962978
T. Onishi, K. Nagaseki, M. Shimada, H. Miyajima, R. Nakata, M. Yamaguchi, J. Murase, H. Hata
{"title":"Advanced EB-cure process and equipment for low-k dielectric","authors":"T. Onishi, K. Nagaseki, M. Shimada, H. Miyajima, R. Nakata, M. Yamaguchi, J. Murase, H. Hata","doi":"10.1109/ISSM.2001.962978","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962978","url":null,"abstract":"Recently IC makers have requested single wafer processes because the number of wafers in 1 lot is small and the size of the wafers are larger. Usually spin on low-k material is used by the furnace (FNC) for long time thermal cure process. A new electron beam (EB) cure equipment and process are developed to improve the mechanical strength of low-k dielectric, to reduce the time of cure process and to reduce thermal budget. By EB curing, JSR LKD (low k dielectric) material (k = 2.9) becomes 1.6 times stronger than conventional film. EB cure also shows considerable merit over FNC in cure time and power consumption for small batch size processing. For single wafer processing, the cure time is reduced from 30 minutes to 2 minutes. The power consumption is less than half of the FNC case for 25 wafer processing. Electric charge up damage is measured and proved not much of a drawback for devices.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121702592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Development of the next generation Si wafer transfer/stock system 新一代硅片转移/储存系统的开发
2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203) Pub Date : 2001-10-08 DOI: 10.1109/ISSM.2001.963023
Y. Kanechika, T. Kawaguchi, M. Nagase, T. Jimbo, M. Yamasaki, M. Hirayama, Y. Shirai, T. Ohmi
{"title":"Development of the next generation Si wafer transfer/stock system","authors":"Y. Kanechika, T. Kawaguchi, M. Nagase, T. Jimbo, M. Yamasaki, M. Hirayama, Y. Shirai, T. Ohmi","doi":"10.1109/ISSM.2001.963023","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963023","url":null,"abstract":"Clean room air contains many kinds of contaminants such as moisture and organic compounds. The device performance is influenced by them, therefore, Si wafers should not be exposed to clean room air. We have developed the next generation Si wafer transfer/stock system using out-gas free advanced resin and CDA (Clean Dry Air). The advanced resin has various advantageous properties for a Si wafer transfer box and stocker. For example, (1) out-gas free, (2) light weight, (3) high transparency, (4) high strength, etc. Using the advanced resin, we have developed a new Si wafer transfer pod, called BORP (Bottom Opening Removal Pod).","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127812456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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