发布求助
文献互助 智能选刊 最新文献

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)最新文献

筛选
英文 中文
New 4-transistor XOR and XNOR designs 新的4晶体管XOR和XNOR设计
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI: 10.1109/APASIC.2000.896899
H. Bui, A. Al-Sheraidah, Yuke Wang
{"title":"New 4-transistor XOR and XNOR designs","authors":"H. Bui, A. Al-Sheraidah, Yuke Wang","doi":"10.1109/APASIC.2000.896899","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896899","url":null,"abstract":"Exclusive-OR and exclusive-NOR gates are important in digital circuits. This paper proposes a new set of low power 4-transistor XOR/XNOR gates. Simulations have been performed on the circuits along with 10 other XOR gates. The results show that the new XOR/XNOR gates consistently consume less power than any other XOR/XNOR gate known at the time of publication. In fact, it consumes up to more than 3 times less power than the complementary CMOS implementation and can have 34% better propagation delay. The static energy-recovery XOR gate, which is the second least power-consuming, dissipates 10% more power than the new gates.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115118532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 99
A 1.0 Gbps clock and data recovery circuit with two-XOR phase-frequency detector 带有双xor相频检测器的1.0 Gbps时钟和数据恢复电路
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI: 10.1109/APASIC.2000.896943
Dong-Hee Kim, Jin-Ku Kang
{"title":"A 1.0 Gbps clock and data recovery circuit with two-XOR phase-frequency detector","authors":"Dong-Hee Kim, Jin-Ku Kang","doi":"10.1109/APASIC.2000.896943","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896943","url":null,"abstract":"This paper describes a 1.0 Gbps clock and data recovery circuit with a simple PFD structure. The proposed circuit is based on a single loop controlled by a Phase Frequency Detector (PFD) which has two-XOR gates. The VCO composed of four differential buffer stages generates eight differential clocks each spaced by 45/spl deg/. The PFD generates the VCO control signal by comparing two different phase clocks and input data. The phase frequency capture range of PFD is decided by VCO operating range which is 380-720 MHz. The circuit operates on 800 Mbps to 1.2 Gbps data rate under 2.5 V supply using 0.25 /spl mu/m CMOS HSPICE simulation.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128597051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low-complexity frame memory compression algorithm and its implementation for MPEG-2 video decoder 一种用于MPEG-2视频解码器的低复杂度帧存储压缩算法及其实现
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI: 10.1109/APASIC.2000.896919
T. Lee, Yong Kim, Sungjae Jang, Hoon Yoo, Jechang Jeong
{"title":"A low-complexity frame memory compression algorithm and its implementation for MPEG-2 video decoder","authors":"T. Lee, Yong Kim, Sungjae Jang, Hoon Yoo, Jechang Jeong","doi":"10.1109/APASIC.2000.896919","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896919","url":null,"abstract":"An algorithm and its implementation to compress video frame data to be stored in external memory are proposed, thereby enabling a reduction of memory requirements and bandwidth. To support random access capability, frames are organized as 1/spl times/8 fixed-length segments, which are used as compression units. For both compression efficiency and low complexity, modified Hadamard transform (MHT) and Golomb-Rice (GR) coding are utilized. The compression ratio is fixed at 50% and objective and subjective video quality assessments are performed. Efficient ASIC implementation including Golomb-Rice encoding/decoding is also proposed to reduce the total compression/decompression latency time.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126098468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
CMOS capacitor coupling logic (C/sup 3/L) circuits CMOS电容耦合逻辑(C/sup 3/L)电路
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI: 10.1109/APASIC.2000.896901
Hong-Yi Huang, Teng-Neng Wang
{"title":"CMOS capacitor coupling logic (C/sup 3/L) circuits","authors":"Hong-Yi Huang, Teng-Neng Wang","doi":"10.1109/APASIC.2000.896901","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896901","url":null,"abstract":"The multi-valued logic has been drawing considerable attention as a promising candidate for building future integrated circuits. The capacitor coupling technique is one of the effective methods to approach the performance issue. In this paper the capacitor coupling logic (C/sup 3/L) circuit to implement CMOS logic gates is proposed. The multiple inputs NAND, NOR, AOI, and OAI gates can be easily realized using the technique. Furthermore, the carry and sum circuit of a full-adder is designed and verified.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128302547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A carry-free 54 b/spl times/54 b multiplier using equivalent bit conversion algorithm 使用等效位转换算法的无携带54b /spl倍/ 54b乘法器
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI: 10.1109/APASIC.2000.896911
Yun Kim, B. Song, J. Grosspietsch, S. Gillig
{"title":"A carry-free 54 b/spl times/54 b multiplier using equivalent bit conversion algorithm","authors":"Yun Kim, B. Song, J. Grosspietsch, S. Gillig","doi":"10.1109/APASIC.2000.896911","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896911","url":null,"abstract":"An equivalent bit conversion algorithm (EBCA) is proposed to eliminate the need for final carry propagation in redundant binary (RB) to normal binary (NB) conversion in the RB multiplier. When the EBCA is applied, conventional power-consuming carry-propagating adders are replaced by simple, minimum-sized converters, and complete carry-free multiplication from input to output is achieved. The proposed method significantly reduces the power and the conversion time in the final adder stage of traditional multipliers. The prototype fabricated in 0.35 /spl mu/m CMOS demonstrates that the 54 b/spl times/54 b multiplier consumes only 53.4 mW at 3.3 V for 74 MHz operation.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121420894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A differential type CMOS phase frequency detector 差分型CMOS相位频率检测器
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI: 10.1109/APASIC.2000.896908
R. Chang, Lung-Chih Kuo
{"title":"A differential type CMOS phase frequency detector","authors":"R. Chang, Lung-Chih Kuo","doi":"10.1109/APASIC.2000.896908","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896908","url":null,"abstract":"We propose a new differential-type CMOS phase frequency detector for a PLL design. The circuit uses two D-FFs and two delay buffers. Besides, it adopts two reset functions R1 and R2 to avoid the UP and DN being logic-1 simultaneously. Thus, any mismatch current of the charge pump circuit will not affect the performance of the PLL. The detector can greatly reduce the dead-zone phenomenon in the phase characteristic, which is important in low-jitter applications. In order to detect the smallest phase error the new detector employs delay buffers to shift the phase error. The circuit is simulated by HSPICE with the 0.35 /spl mu/m CMOS technology.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"228 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131419145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Analysis and implementation of interface for heterogeneous system 异构系统接口的分析与实现
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI: 10.1109/APASIC.2000.896930
Hwisung Jung, M. Lee
{"title":"Analysis and implementation of interface for heterogeneous system","authors":"Hwisung Jung, M. Lee","doi":"10.1109/APASIC.2000.896930","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896930","url":null,"abstract":"We designed asynchronous event logic library with 0.25 /spl mu/m CMOS technology and high-speed asynchronous FIFO operating at 1.6 GHz. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for freeing of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, we implemented high-speed 32 bit-interface chip for heterogeneous system. The size of the core is about 1.1 mm/spl times/1.1 mm.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130025812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A QPSK/16 QAM receiver chip for LMDS application 一种用于LMDS的QPSK/16 QAM接收芯片
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI: 10.1109/APASIC.2000.896945
K. Park, D. Shin, Jun S. Lee, M. Sunwoo
{"title":"A QPSK/16 QAM receiver chip for LMDS application","authors":"K. Park, D. Shin, Jun S. Lee, M. Sunwoo","doi":"10.1109/APASIC.2000.896945","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896945","url":null,"abstract":"This paper presents a QPSK/16 QAM down stream receiver ASIC chip for LMDS (Local Multipoint Distribution Services) applications. The proposed LMDS chip consists of a blind equalizer, a timing recovery block and a carrier recovery block. The blind equalizer uses a DFE (Decision Feedback Equalizer) structure using CMA (Constant Modulus Algorithm). The symbol timing recovery uses the modified parabolic interpolator and the decision-directed carrier recovery is used to remove the carrier frequency offset, phase offset and phase jitter. The implemented LMDS receiver can support four data rates, 10, 20, 30 and 40 Mbps and can accommodate the symbol rate up to 10 Mbaud. This symbol rate is faster than existing QAM receivers.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130167541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A dynamic TLB management structure to support different page sizes 支持不同页面大小的动态TLB管理结构
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI: 10.1109/APASIC.2000.896967
Jung-Hoon Lee, Jang-Soo Lee, Shin-Dug Kim
{"title":"A dynamic TLB management structure to support different page sizes","authors":"Jung-Hoon Lee, Jang-Soo Lee, Shin-Dug Kim","doi":"10.1109/APASIC.2000.896967","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896967","url":null,"abstract":"Translation look-aside buffers (TLBs) are small caches to speed-up address translation in processors with virtual memory. There are many methods for improving TLB performance, such as increasing the number of entries in TLB and supporting large page or multiple page sizes. The best way is to support multiple page sizes, but any operating system doesn't support multiple page sizes in user mode. Also software must select a proper page-size assignment policy to take advantage of the larger pages. So, we propose a new structure of TLB supporting two pages to obtain the effect of multiple page sizes with high performance and at low cost without operating system support. According to result of comparison and analysis, the proposed method with fewer entries results in similar performance compared with the conventional TLB with many entries. Also in the case of same area size, it is shown that miss ratio of the proposed TLB can be reduced by as much as 90% comparing with conventional fully-associative TLB.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131086444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The design and implementation of CalmlRISC32 floating point unit CalmlRISC32浮点单元的设计与实现
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI: 10.1109/APASIC.2000.896974
C. Jeong, W. Park, Sang-Woo Kim, T. Han
{"title":"The design and implementation of CalmlRISC32 floating point unit","authors":"C. Jeong, W. Park, Sang-Woo Kim, T. Han","doi":"10.1109/APASIC.2000.896974","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896974","url":null,"abstract":"The CalmRISC32 FPU is RISC style coprocessor for embedded systems. It supports IEEE-754 standard single precision addition/subtraction, floating-point multiplication, floating-point division, format conversion, comparison, rounding, and load/store. It also supports four rounding modes, and precise exception. It can execute and complete instructions out of order if some constraint is resolved-data dependency, resource conflict, and exception prediction. Standard cell base design technique is used to save design time and cost. First prototype is running at about 70 Mhz with worst-case delay in gate level simulation.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128975400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信