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Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)最新文献

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Rapid prototyping of parallel processing systems on TESH network TESH网络上并行处理系统的快速原型设计
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676663
B. M. Maziarz, V. Jain
{"title":"Rapid prototyping of parallel processing systems on TESH network","authors":"B. M. Maziarz, V. Jain","doi":"10.1109/IWRSP.1998.676663","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676663","url":null,"abstract":"The paper discusses implementation of advanced numerical and image-processing applications on a multiprocessor system. With a view toward 'coarse-grain' rapid prototyping, the authors implement two diverse applications onto a common framework, i.e. MAC type processors interconnected by a TESH network. TESH (Tori connected mESHes) is a recently developed interconnection network. It is hierarchical, thus allowing exploitation of computation locality as well as easy expansion, which permits efficient VLSI/ULSI realization, and appears to be well suited for 3-D VLSI/ULSI implementation. Specifically, the paper develops parallel implementation of (a) real-time solution of partial differential equations and (b) 2D wavelet transform, in such a way so as to completely hide the communication overhead. It is shown that the performance of TESH implemented algorithms is comparable to the MESH based algorithm. However, TESH networks are much easier to implement because of the significantly reduced wiring than MESH networks.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"606 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132274442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Real-time prototyping in microprocessor/accelerator symbiosis 微处理器/加速器共生中的实时原型设计
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676665
J. Becker, R. Hartenstein
{"title":"Real-time prototyping in microprocessor/accelerator symbiosis","authors":"J. Becker, R. Hartenstein","doi":"10.1109/IWRSP.1998.676665","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676665","url":null,"abstract":"The paper introduces a new coarse-grained dynamically reconfigurable hardware platform and a general model for prototyping cooperating host/accelerator platforms under real-time constraints. A new parallelizing compilation method derived from this model is explained, whereas novel \"vertical\" parallelization techniques are applied for such structural programmable accelerators. For performing real-time constraint analysis and fulfilment the process of task performance estimation for host/accelerator executions is explained. Additionally the paper explained the overall execution time estimation of multi-task applications.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134232276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Reusable architecture templates and automatic specification mapping for the efficient implementation of ATM protocols 可重用的体系结构模板和自动规范映射，用于ATM协议的有效实现
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676667
N. Voros, E. Mariatos, M. Birbas, A. Birbas, N. Petrellis, S. Batistatos
{"title":"Reusable architecture templates and automatic specification mapping for the efficient implementation of ATM protocols","authors":"N. Voros, E. Mariatos, M. Birbas, A. Birbas, N. Petrellis, S. Batistatos","doi":"10.1109/IWRSP.1998.676667","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676667","url":null,"abstract":"The paper presents an algorithm for the automatic mapping of problem specifications to existing architecture templates. The proposed methodology supports the combination of existing architectural components in order to achieve an efficient specification mapping to the most appropriate architecture, driven by the constraints posed by the initial problem. The production of non-fixed templates that evolve over the development of the various products is exhibited through the design of an ATM adapter card, while the concept of template reusability is presented through the design of an ATM protocol stack for wireless networks.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128251164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Truly rapid prototyping requires high level synthesis 真正的快速原型需要高水平的综合
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676676
Goran Doncev, M. Leeser, Shantanu Tarafdar
{"title":"Truly rapid prototyping requires high level synthesis","authors":"Goran Doncev, M. Leeser, Shantanu Tarafdar","doi":"10.1109/IWRSP.1998.676676","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676676","url":null,"abstract":"Truly rapid prototyping requires a combination of abstract design tools and field-programmable logic. In this paper, we study the application of high-level synthesis (HLS) in the design of field-programmable gate array (FPGA) based systems. Our experience using the Synopsys Behavioral Compiler to map designs onto the Altera RIPP10 board shows that HLS allows for a level of design space exploration that is unrealizable with register transfer level techniques. In addition, the use of HLS tools allows designers to prototype their designs with high-quality results and much faster design turnaround times. We discuss these issues in the context of our experiences with mapping a dual-tone multi-frequency (DTMF) receiver onto the RIPP10 board.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128344638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The Plastic Cell Architecture for dynamic reconfigurable computing 动态可重构计算的塑性单元结构
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676666
Hideyuki Ito, K. Oguri, Kouichi Nagami, Ryusuke Konishi, Tsunemichi Shiozawa
{"title":"The Plastic Cell Architecture for dynamic reconfigurable computing","authors":"Hideyuki Ito, K. Oguri, Kouichi Nagami, Ryusuke Konishi, Tsunemichi Shiozawa","doi":"10.1109/IWRSP.1998.676666","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676666","url":null,"abstract":"The authors explain the dynamic manipulation of the object as an essential function which a general purpose computer should have. Introducing this property, they propose a general purpose reconfigurable computer architecture to obtain both performance of the wired logic and generality of the program logic. Since the proposing reconfigurable logic device is a mesh structure of the cell of high plasticity, they name it Plastic Cell Architecture (PCA). Each cell has a dual structure consisting of the built-in part and the plastic part. The plastic part performs as a logic element which constructs the wired logic. And the built-in part takes charge of the reconfiguration. They describe the structure of the cell and the necessary function for the built-in part.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"os-53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127791639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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