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Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)最新文献

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Behavioral emulation of synthesized RT-level descriptions using VLIW architectures 使用VLIW体系结构的综合rt级描述的行为仿真
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676671
T. Buchholz, G. Haug, U. Kebschull, G. Koch, W. Rosenstiel
{"title":"Behavioral emulation of synthesized RT-level descriptions using VLIW architectures","authors":"T. Buchholz, G. Haug, U. Kebschull, G. Koch, W. Rosenstiel","doi":"10.1109/IWRSP.1998.676671","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676671","url":null,"abstract":"Describes techniques that allow VLIW architectures to be used for the behavioral emulation of RT-level descriptions. The starting point of the techniques is a behavioral description at the algorithmic level, e.g. VHDL. This description is transformed into RT-level descriptions of the datapath and controller. The controller is given as a finite state machine. We show how to map these descriptions onto assembly code that can be executed on a VLIW microprocessor. We found the Texas Instruments TMS320C6x series of DSP chips to be suitable candidates for the mapping.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127089375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Hardware, software and mechanical cosimulation for automotive applications 汽车应用的硬件、软件和机械协同仿真
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676692
P. LeMarrec, C. Valderrama, Fabiano Hessel, A. Jerraya, M. Attia, O. Cayrol
{"title":"Hardware, software and mechanical cosimulation for automotive applications","authors":"P. LeMarrec, C. Valderrama, Fabiano Hessel, A. Jerraya, M. Attia, O. Cayrol","doi":"10.1109/IWRSP.1998.676692","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676692","url":null,"abstract":"The design of automotive systems requires the joint design of hardware, software and micro-mechanical components. In traditional design approaches the different parts are designed by separate groups and the integration of the overall system is made at the final stage. This scheme may induce extra delays and costs because of interfacing problems. The paper presents a new automotive system design approach that offers many advantages including efficient design flow and shorter time to market. The key idea of our approach is to allow for early validation of the overall system through co-simulation. The design starts with a high level specification of each part. In our approach, software is described in C, hardware is described in VHDL and mechanical parts are described in MATLAB. A C-VHDL-MATLAB co-simulation is then used for functional validation of the initial specification. During the design process, the hardware and software parts may be refined using specific techniques and tools. The refinement steps are also validated through co-simulation. In this approach we use two kinds of co-simulation: untimed co-simulation is used for functional validation and timed co-simulation for real time validation. The paper describes the design approach and its successful application to an example from the automotive industry.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114155128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
The video and image processing emulation system VIPES 视频图像处理仿真系统VIPES
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676687
Holger Kropp, Carsten Reuter, P. Pirsch
{"title":"The video and image processing emulation system VIPES","authors":"Holger Kropp, Carsten Reuter, P. Pirsch","doi":"10.1109/IWRSP.1998.676687","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676687","url":null,"abstract":"We present a real time emulation system for complete video processing schemes. Our emulation system is based on a commercial FPGA emulator and related software. To meet real time constraints, we have extended this emulation environment by dedicated video interfaces, efficient flexible FPGA macros, and a modified design flow. The feasibility of this methodology is shown for a two dimensional discrete cosine transform, resulting in a reduction of approximately 58% in terms of FPGA resources. The emulation frequency improves by 33%. Furthermore, by emulating different coefficient word widths and subjective evaluation of image quality, it could be shown that a word width of 10 bits is sufficient for our design.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133728978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Run-time monitoring of communication activities in a rapid prototyping environment 在快速原型环境中对通信活动进行运行时监视
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676668
A. Kirschbaum, J. Becker, M. Glesner
{"title":"Run-time monitoring of communication activities in a rapid prototyping environment","authors":"A. Kirschbaum, J. Becker, M. Glesner","doi":"10.1109/IWRSP.1998.676668","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676668","url":null,"abstract":"Architectural decisions in embedded systems design are often based on assumptions about properties of the communication channels. For validating them rapid prototyping combined with run-time monitoring plays a major role. The authors present HarMonIC-a reconfigurable hardware monitoring system for the run-time observation of communication channels. They show how HarMonIC can be used to significantly improve debugging, performance evaluation, and design space exploration of communication architectures in embedded systems.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127754314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
OMI-compliant model for virtual emulation 符合omi的虚拟仿真模型
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676670
D. Dozza, R. Rambaldi, M. Borgatti, R. Guerrieri
{"title":"OMI-compliant model for virtual emulation","authors":"D. Dozza, R. Rambaldi, M. Borgatti, R. Guerrieri","doi":"10.1109/IWRSP.1998.676670","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676670","url":null,"abstract":"In this paper, the virtual emulation problem is addressed. We give sufficient conditions for a digital system to be emulable. Moreover, we present sufficient conditions under which system emulation can degenerate from an event-driven to a faster cycle-based simulation. The OMI (Open Model Interface), an emerging standard modeling interface for digital systems, has been considered to develop an emulation system that is usable in every OMI-compliant simulation environment.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121373433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A data-flow oriented co-design for reconfigurable systems 面向数据流的可重构系统协同设计
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676693
J. David, J. Legat
{"title":"A data-flow oriented co-design for reconfigurable systems","authors":"J. David, J. Legat","doi":"10.1109/IWRSP.1998.676693","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676693","url":null,"abstract":"Multi FPGA systems are mainly composed of programmable logic devices and external memory. Up to date FPGAs also contain embedded static RAMs, which have shorter access time than the external SRAMs. The paper presents a dataflow oriented algorithm that makes use of the small embedded memories as local caches for data processing. The algorithm offers a high level of parallelism and efficient use of processing resources. This is done in the context of hardware-software co-design. The objective is to automatically implement parts of C code requiring high processing rates on a reconfigurable system. An example of implementation on a 400 Kgates 8 Mbytes multi FPGA system is described.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115908401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An open simulation and modelling environment for embedded real-time systems 嵌入式实时系统的开放式仿真和建模环境
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676675
W. V. Almsick, T. Drabe, W. Daehn, C. Müller-Schloer
{"title":"An open simulation and modelling environment for embedded real-time systems","authors":"W. V. Almsick, T. Drabe, W. Daehn, C. Müller-Schloer","doi":"10.1109/IWRSP.1998.676675","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676675","url":null,"abstract":"An open design and simulation environment for embedded real-time systems is presented. It focuses on validation and observation of combined hardware/software systems and easy integration of new tools. The simulation and modelling mechanisms are detailed, together with their respective interactions. Initial experiments and performance results are described. The work is part of the OMI/TOOLS project funded by the European Community.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121499827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Emulating large designs on small reconfigurable hardware 在小型可重构硬件上模拟大型设计
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676669
Karthikeya M. Gajjala Purna, D. Bhatia
{"title":"Emulating large designs on small reconfigurable hardware","authors":"Karthikeya M. Gajjala Purna, D. Bhatia","doi":"10.1109/IWRSP.1998.676669","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676669","url":null,"abstract":"FPGA based hardware emulation is becoming very popular for checking the functional correctness of designs prior to fabrication. A design is partitioned and mapped on a programmable hardware system that consists of several FPGAs. Typically, as the design size increases, the utilization of FPGA devices tends to fall rapidly. This demands large amounts of hardware resources for emulating large designs. The authors have demonstrated a methodology for mapping huge designs by partitioning, scheduling, and proper controlling through software on small reconfigurable or programmable hardware platforms. They explore the usage of time domain as a viable alternative to space domain for logic emulation. The methodology is demonstrated with real executing examples.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121834495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Using CDIF for concept-oriented rapid prototyping of electronic systems 利用CDIF进行面向概念的电子系统快速原型设计
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676689
A. Burst, M. Wolff, M. Kühl, K. Müller-Glaser
{"title":"Using CDIF for concept-oriented rapid prototyping of electronic systems","authors":"A. Burst, M. Wolff, M. Kühl, K. Müller-Glaser","doi":"10.1109/IWRSP.1998.676689","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676689","url":null,"abstract":"An open environment for heterogeneous system design is presented supporting all design phases. Our approach separates front end tools with structural and behavioral modeling from back end tools for analysis, simulation and emulation. This separation is realized with the emerging CASE data interchange format CDIF. Though CDIF is intended as an interchange format for the interchange of modeling data between modeling tools, CDIF can also serve as an appropriate basis for back end tools. Our approach supports an overall system design and results in a unique representation of modeling data and a modeling technique based, tool independent analysis, simulation and emulation. In addition, we discuss the suitability of CDIF and present results for several implementations.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128306368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Towards a rapid prototyping by linking design, implementation and debugging in real-time parallel systems 通过将实时并行系统的设计、实现和调试联系起来，实现快速原型
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676691
C. E. Morón, José R. P. Ribeiro, N. C. D. Silva
{"title":"Towards a rapid prototyping by linking design, implementation and debugging in real-time parallel systems","authors":"C. E. Morón, José R. P. Ribeiro, N. C. D. Silva","doi":"10.1109/IWRSP.1998.676691","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676691","url":null,"abstract":"Due to the culture of sequential programming, the lack of tools and the inherent difficulties of parallel programming, most programmers find it hard to design and evaluate real time parallel programs. As a result, a major problem found in the development of real time parallel systems is the difficulty to produce rapid prototypes of the application and frequently the development of these types of systems, is behind schedule. The paper presents a visual environment which should be able to provide continuity in the development of projects using the most common development methods, traditional or object oriented, by offering support during the phases of implementation, debugging and testing. The environment has a visual interface with the user and the main aim is to facilitate the learning process in the generation and debugging of source code of applications developed for parallel kernels, in particular for Virtuoso (Virtual Single Processor Programming System-Virtuoso is a trademark of Eonic Systems-http://www.eonic.com). The environment is composed of four tools: a Parallel Program Generator, a Worst Case Execution Time Analyser, a Scheduling Analyser, and a Parallel Debugger. The first version of the tool is available for download from http://www.dc.ufscar.br/tev/tev.html and was released as Teaching Environment for Virtuoso (TEV).","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121831012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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