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Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)最新文献

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The STEP standard as an approach for design and prototyping STEP标准作为设计和原型的方法
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676674
A. Plantec, V. Ribaud
{"title":"The STEP standard as an approach for design and prototyping","authors":"A. Plantec, V. Ribaud","doi":"10.1109/IWRSP.1998.676674","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676674","url":null,"abstract":"STEP is an ISO standard (ISO-10303) for the computer-interpretable representation and exchange of product data. Parts of STEP standardize conceptual structures and the usage of information in generic or specific domains. The standardization process of these constructs is an evolutionary approach, which uses generated prototypes at different phases of the process. This paper presents a method for the building of prototype generators, inspired by this standardization process, together with a tool used to support the method. Throughout the stages of model integration, the embedded logic of the prototype generators is defined. The successive stages focus on data model integration, but this integration relies on a common agreement about the construct functionalities under elaboration.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121270986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Code generation of data dominated DSP applications for FPGA targets 数据代码生成占DSP应用的主导地位，以FPGA为目标
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676686
J. Dalcolmo, R. Lauwereins, M. Adé
{"title":"Code generation of data dominated DSP applications for FPGA targets","authors":"J. Dalcolmo, R. Lauwereins, M. Adé","doi":"10.1109/IWRSP.1998.676686","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676686","url":null,"abstract":"The VHDL code generator of the GRAPE rapid prototyping and design environment has been extended to support a much wider range of data dominated applications. We describe the approach taken to implement CSDF applications on FPGAs, including the automatic code generation for task communication and scheduling on FPGAs alone or in conjunction with DSP processors. The implementation choices are discussed, and a comparison to manual code generation is made.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127525654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Real time prototyping method and a case study 实时原型方法和案例研究
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676662
H. Krupnova, D. Vu, G. Saucier, M. Boubal
{"title":"Real time prototyping method and a case study","authors":"H. Krupnova, D. Vu, G. Saucier, M. Boubal","doi":"10.1109/IWRSP.1998.676662","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676662","url":null,"abstract":"The paper presents a strategy for high-speed prototyping on FPGAs. The traditional \"glue\" synthesis strategy may not be sufficient for obtaining FPGA prototypes working at real speed. A key possibility to accelerate the performance of FPGA designs is the utilisation of the architectural features of modern FPGAs. To do this, no \"push-button\" solutions exists. The way to do this is to process one by one the critical blocks of the design and to decide about the implementation strategy for each block. As an example, a case study of a microprocessor circuit is presented. The microprocessor should be able to work in real time at 10 MHz frequency. To reach this speed in the Altera FLEX 10 KA technology, a special implementation strategy was elaborated for the microprocessor's RAM and ALU blocks.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132736929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A prototyping system for high performance communication systems 高性能通信系统的原型系统
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676673
Matthias Dörfel, R. Hofmann
{"title":"A prototyping system for high performance communication systems","authors":"Matthias Dörfel, R. Hofmann","doi":"10.1109/IWRSP.1998.676673","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676673","url":null,"abstract":"Presents a prototyping platform for high-performance communication systems together with a design methodology. Based on a formal design entry and nonfunctional design goals such as execution time and overall system cost, a software/hardware partitioning is generated and its performance is estimated with formal models. Valid partitionings are then implemented on a prototyping platform which is based on a heterogeneous multiprocessor system and a reconfigurable FPGA board. Using model-based optimization and monitoring, each partitioning is evaluated and the results are fed back in the generation and estimation of new partitionings.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132883050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
APICES-rapid application development with graph pattern 使用图形模式快速开发应用程序
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676664
A. Bredenfeld
{"title":"APICES-rapid application development with graph pattern","authors":"A. Bredenfeld","doi":"10.1109/IWRSP.1998.676664","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676664","url":null,"abstract":"The author present the novel software design environment APICES. It is specifically tailored to support rapid application development based on network like data structures which are typical for CAD tools, system level design tools or DSP applications. APICES is based on graph patterns. These graph patterns offer high-level functionality for beyond manipulation of simple graphs consisting of nodes and edges. By making graph patterns re-usable within an object-oriented framework architecture and by offering multi-target code generators the author is able to provide a powerful environment for prototyping and rapid development of graph-based applications. The author demonstrates the productivity gains and the benefits of APICES by rapid application development of a multi-rate digital signal processing tool.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114077245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Virtual prototyping of a digital neural current controller 数字神经电流控制器的虚拟样机
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676688
A. Dinu, M. Cirstea, M. McCormick
{"title":"Virtual prototyping of a digital neural current controller","authors":"A. Dinu, M. Cirstea, M. McCormick","doi":"10.1109/IWRSP.1998.676688","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676688","url":null,"abstract":"The paper describes a significant case study of virtual prototyping in modern digital electronics. It outlines the design process of a neural predictive current controller for VSI-PWM inverters. MATLAB simulations of power system behaviour were initially performed to check the viability of the principles underlying the operation of the new controller. The controller was designed and tested using Viewlogic/Xilinx software for FPGA design/implementation. The intensive use of C++ programming to generate the required VHDL model of the neural networks considerably accelerated the design process.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114395458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Testing prototypes validity to enhance code reuse 测试原型的有效性以增强代码重用
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676661
Didier Buchs, A. Diagne, F. Kordon
{"title":"Testing prototypes validity to enhance code reuse","authors":"Didier Buchs, A. Diagne, F. Kordon","doi":"10.1109/IWRSP.1998.676661","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676661","url":null,"abstract":"The complexity of distributed systems is a problem when designers want to evaluate their safety and liveness. Often, they are built by integration of existing components with newly developed ones. Actually it is valuable to handle the integration of external pieces of software in the specification and testing activities. However it is difficult to validate them formally unless doing reverse-engineering (which is a heavy procedure). The paper proposes to use structured formal specifications to generate a reasonable set of tests that evaluate behavior of software components in order to get an answer to both questions. To do so, the authors use the description of components external behavior and express it using the OF-Class formalism (an encapsulation of colored Petri nets). Test patterns are generated using an appropriate formalism, HML logic, and they exploit various hypotheses corresponding to a user's testing procedure.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115347030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Rapid system prototyping for real-time design validation 用于实时设计验证的快速系统原型
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676677
M. Courtoy
{"title":"Rapid system prototyping for real-time design validation","authors":"M. Courtoy","doi":"10.1109/IWRSP.1998.676677","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676677","url":null,"abstract":"System emulation technology enables users to rapidly prototype HDL-based designs on programmable hardware before committing their designs to production. In this paper, we show that this methodology is particularly viable for at-speed verification of communications designs. We show how complimentary tools can be used to generate HDL code for a digital wireless communications system. Then we consider how this design can be implemented and evaluated using a rapid prototyping methodology. Synthesis produces a gate-level specification for implementation in FPGAs which are combined with other components in the Aptix rapid prototyping environment. Issues discussed include: software tool flows, prototype hardware assembly, system performance and debugging.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114649410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Rapid design of discrete orthonormal wavelet transforms 离散正交小波变换的快速设计
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676683
S. Masud, J. McCanny
{"title":"Rapid design of discrete orthonormal wavelet transforms","authors":"S. Masud, J. McCanny","doi":"10.1109/IWRSP.1998.676683","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676683","url":null,"abstract":"A methodology which allows a non specialist to rapidly design silicon wavelet transform cores has been developed. This methodology is based on a generic architecture utilising time interleaved coefficients for the wavelet transform filters. The architecture is scaleable and it has been parameterised in terms of wavelet family, wavelet type, data word length and coefficient word length. The control circuit is designed in such a way that the cores can also be cascaded without any interface glue logic for any desired level of decomposition. This parameterisation allows the use of any orthonormal wavelet family, thereby extending the design space for improved transformation from algorithm to silicon. Case studies for stand alone and cascaded silicon cores for single and multi stage analysis respectively are reported. The typical design time to produce silicon layout of a wavelet based system has been reduced by an order of magnitude. The cores are comparable in area and performance to hand crafted designs. The designs have been captured in VHDL so they are portable across a range of foundries and are also applicable to FPGA and PLD implementations.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127436815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Performance evaluation tool for rapid prototyping of hardware-software codesigns 用于硬件软件协同设计快速原型的性能评估工具
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676695
Karam S. Chatha, R. Vemuri
{"title":"Performance evaluation tool for rapid prototyping of hardware-software codesigns","authors":"Karam S. Chatha, R. Vemuri","doi":"10.1109/IWRSP.1998.676695","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676695","url":null,"abstract":"Performance evaluation is essential for tradeoff analysis during rapid prototyping. Existing performance evaluation strategies based on co-simulation and static analysis are either too slow or error prone. We therefore present an intermediate approach based on profiling and scheduling for rapid prototyping of hardware-software codesigns. Our performance evaluation tool obtains representative task timings by profiling which is done simultaneously with system specification. During design space exploration the tool obtains performance estimates by using well known scheduling and novel retiming heuristics. It is capable of obtaining both nonpipelined and pipelined schedules. The tool includes an area estimator which calculates the amount of hardware area required by the design by taking resource sharing between different hardware tasks into account. The tool also allows the user to evaluate the performance of a particular schedule with different task timings. In contrast to co-simulation and static analysis, the tool is able to provide fast and accurate performance estimates. The effectiveness of the tool in a rapid prototyping environment is demonstrated by a case study.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131330618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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