Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)最新文献

HW/SW cosynthesis using statecharts and symbolic timing diagrams 使用状态图和符号时序图的硬件/软件协同

Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676694

Karsten Lüth, Jürgen Niehaus, T. Peikenkamp

引用次数: 13

Rapid prototyping technology accelerates software development for complex network systems 快速原型技术加速了复杂网络系统的软件开发

Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676678

Veena Bhatia, Sofia Shtil

引用次数: 4

A technique for combined virtual prototyping and hardware design 虚拟样机与硬件设计相结合的技术

Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676685

P. Schaumont, G. Vanmeerbeeck, E. Watzeels, S. Vernalde, M. Engels, I. Bolsens

引用次数: 1

Performance and interface buffer size driven behavioral partitioning for embedded systems 性能和接口缓冲区大小驱动的嵌入式系统行为分区

Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676679

Ta-Cheng Lin, S. M. Sait, W. Cyre

{"title":"Performance and interface buffer size driven behavioral partitioning for embedded systems","authors":"Ta-Cheng Lin, S. M. Sait, W. Cyre","doi":"10.1109/IWRSP.1998.676679","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676679","url":null,"abstract":"One of the major differences in partitioning for co-design is in the way the communication cost is evaluated. Generally, the size of the edge cut-set is used. When communication between components is through buffered channels, the size of the edge cut-set is not adequate to estimate the buffer size. A second important factor to measure the quality of partitioning is the system delay. Most partitioning approaches use the number of nodes/functions in each partition as constraints and attempt to minimize the communication cost. The data dependencies among nodes/functions and their delays are not considered. In this paper, we present partitioning with two objectives: (1) buffer size, which is estimated by analyzing the data flow patterns of the control data flow graph (CDFG) and solved as a clique partitioning problem, and (2) the system delay that is estimated using list scheduling. We pose the problem as a combinatorial optimization and use an efficient non-deterministic search algorithm, called the problem-space genetic algorithm, to search for the optimum. Experimental results indicate that, according to a proposed quality metric, our approach can attain an average 87% of the optimum for two-way partitioning.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114885625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

RIFLE-62: a flexible environment for prototyping dynamically reconfigurable systems 步枪-62:一个灵活的环境原型动态可重构系统

Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676681

M. Vasilko, D. Long

引用次数: 9

Implementation of an RTLS blind equalization algorithm on DSP 基于DSP的RTLS盲均衡算法的实现

Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676684

P. Vandaele, G. Rombouts, M. Moonen

引用次数: 1

A library of memory controllers for an image processing prototyping system 一个图像处理原型系统的内存控制器库

Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676690

F. Lisa-Mingo, J. Carrabina

引用次数: 2

Rapid prototyping of a co-processor based engine knock detection system 基于协处理器的发动机爆震检测系统的快速原型设计

Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676680

A. Kirschbaum, S. Ortmann, M. Glesner

引用次数: 8

An extensible, low cost rapid prototyping environment based on a reconfigurable set of FPGAs 一个可扩展的，低成本的快速原型环境，基于一组可重构的fpga

Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676672

K. Adaos, G. Alexiou, N. Kanopoulos

引用次数: 4

FLYSIG: dataflow oriented delay-insensitive processor for rapid prototyping of signal processing 面向数据流的延迟不敏感处理器，用于信号处理的快速原型

Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI: 10.1109/IWRSP.1998.676682

W. Hardt, B. Kleinjohann

{"title":"FLYSIG: dataflow oriented delay-insensitive processor for rapid prototyping of signal processing","authors":"W. Hardt, B. Kleinjohann","doi":"10.1109/IWRSP.1998.676682","DOIUrl":"https://doi.org/10.1109/IWRSP.1998.676682","url":null,"abstract":"As the one-chip integration of HW modules designed by different companies becomes more and more popular, reliability of a HW design and evaluation of the timing behavior during the prototype stage are absolutely necessary. One way to guarantee reliability is the use of robust design styles, e.g., delay insensitivity. For early timing evaluation, two aspects must be considered: a) the timing needs to be proportional to technology variations, and b) the implemented architecture should be identical for prototype and target. The first can be met also by delay insensitive implementation. The latter one is the key point. A unified architecture is needed for prototyping as well as implementation. Our new approach to rapid prototyping of signal processing tasks is based on a configurable, delay insensitive implemented processor called FLYSIG (dataflow oriented delay-insensitive signal processing). In essence, the FLYSIG processor can be understood as a complex FPGA where the CLBs are substituted by bit serial operators. The general concept is detailed and first experimental results are given for demonstration of the main advantages: delay insensitive design style, direct correspondence between prototyping and target architecture, high performance and reasonable shortening of the design cycle.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130578561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10