2016 IEEE 34th International Conference on Computer Design (ICCD)最新文献_第3页

A novel simulation based approach for trace signal selection in silicon debug 一种新的基于仿真的硅调试中跟踪信号选择方法

2016 IEEE 34th International Conference on Computer Design (ICCD) Pub Date : 2016-10-01 DOI: 10.1109/ICCD.2016.7753280

Prabanjan Komari, R. Vemuri

{"title":"A novel simulation based approach for trace signal selection in silicon debug","authors":"Prabanjan Komari, R. Vemuri","doi":"10.1109/ICCD.2016.7753280","DOIUrl":"https://doi.org/10.1109/ICCD.2016.7753280","url":null,"abstract":"With the fabrication technology fast approaching 7nm, post-silicon validation has become an integral part of integrated circuit design to capture and eliminate functional bugs that escape pre-silicon validation. The major roadblock in post-silicon functional verification is limited observability of internal signals in a design. A possible solution to address this roadblock is to make use of embedded memories on chip called trace buffers. The amount of debug data that can be acquired from the trace buffer depends on its width and depth. The width of the trace buffer limits the number of signals that can be traced and the depth of the trace buffer limits the number of samples that can be acquired. Using the acquired data from the trace buffer, the values of other nodes in the circuit can be reconstructed. These trace buffers have limited area, hence only a few critical signals can be recorded by it. In this work we used the simulated annealing heuristic to select trace signals. We developed this idea from the fact that trace signal selection can be viewed as a bi-partitioning problem, the set of flip-flops being tapped onto the trace buffer is one partition and remaining flip-flops form the other partition. Experimental results demonstrate that our approach can result in better restoration ratio compared to the state-of-the-art techniques.","PeriodicalId":297899,"journal":{"name":"2016 IEEE 34th International Conference on Computer Design (ICCD)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128998878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Parallelizing Latent Semantic Indexing using an FPGA-based architecture 使用基于fpga的架构并行化潜在语义索引

2016 IEEE 34th International Conference on Computer Design (ICCD) Pub Date : 2016-10-01 DOI: 10.1109/ICCD.2016.7753321

Xinying Wang, Joseph Zambreno

引用次数: 0

Cryptographic vote-stealing attacks against a partially homomorphic e-voting architecture 针对部分同态电子投票架构的加密投票窃取攻击

2016 IEEE 34th International Conference on Computer Design (ICCD) Pub Date : 2016-10-01 DOI: 10.1109/ICCD.2016.7753275

N. G. Tsoutsos, M. Maniatakos

引用次数: 4

What does ultra low power requirements mean for side-channel secure cryptography? 超低功耗要求对侧信道安全加密意味着什么?

2016 IEEE 34th International Conference on Computer Design (ICCD) Pub Date : 2016-10-01 DOI: 10.1109/ICCD.2016.7753359

Monodeep Kar, Arvind Singh, Anand Rajan, V. De, S. Mukhopadhyay

引用次数: 3

Energy-aware scheduling of conditional task graphs with deadlines on MPSoCs mpsoc上带截止日期的条件任务图的能量感知调度

2016 IEEE 34th International Conference on Computer Design (ICCD) Pub Date : 2016-10-01 DOI: 10.1109/ICCD.2016.7753289

Umair Ullah Tariq, Hui Wu

{"title":"Energy-aware scheduling of conditional task graphs with deadlines on MPSoCs","authors":"Umair Ullah Tariq, Hui Wu","doi":"10.1109/ICCD.2016.7753289","DOIUrl":"https://doi.org/10.1109/ICCD.2016.7753289","url":null,"abstract":"We investigate the problem of scheduling a set of non-pre-emptive tasks with individual deadlines and conditional precedence constraints on MPSoCs (MultiProcessor System-on-Chips) with shared memory such that the total processor energy consumption of all the tasks in each scenario is minimized under two power models, namely the dynamic power model and the total power model, and propose a unified two-phase approach. The approach consists of an offline task scheduler and an online task scheduler. The offline scheduler uses a novel priority scheme to assign each task to a processor, constructs a global schedule, and uses convex NLP (NonLinear Programming) to compute an optimal speed for each task. The online task scheduler dynamically performs task reallocation and task rescheduling, and reassigns a speed to each task to utilize the slack time generated by individual scenarios. We have compared our approach with two state-of-the-art approaches by using 23 benchmarks. The experimental result show that the average improvement and the maximum improvement of our approach over the approach proposed by Ge et al. are 19.2% and 28.6%, respectively, and the average improvement and the maximum improvement over the approach proposed by Malani et al. are 53.2% and 74.2%, respectively.","PeriodicalId":297899,"journal":{"name":"2016 IEEE 34th International Conference on Computer Design (ICCD)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127656111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

MASkIt: Soft error rate estimation for combinational circuits 组合电路的软错误率估计

2016 IEEE 34th International Conference on Computer Design (ICCD) Pub Date : 2016-10-01 DOI: 10.1109/ICCD.2016.7753348

Martí Anglada, R. Canal, Juan L. Aragón, Antonio González

引用次数: 14

Guided lightweight Software test qualification for IP integration using Virtual Prototypes 指导轻量级软件测试资格的IP集成使用虚拟原型

2016 IEEE 34th International Conference on Computer Design (ICCD) Pub Date : 2016-10-01 DOI: 10.1109/ICCD.2016.7753347

Daniel Große, H. M. Le, Muhammad Hassan, R. Drechsler

{"title":"Guided lightweight Software test qualification for IP integration using Virtual Prototypes","authors":"Daniel Große, H. M. Le, Muhammad Hassan, R. Drechsler","doi":"10.1109/ICCD.2016.7753347","DOIUrl":"https://doi.org/10.1109/ICCD.2016.7753347","url":null,"abstract":"Software-Driven Verification (SDV) has the promise to significantly reduce the overall time and effort for the task of IP integration and verification. With the help of SystemC Virtual Prototypes (VPs), SW tests to verify the (new) integrated IP blocks and the HW/SW integration can be developed in an early design stage and reused in the subsequent steps. However, the crucial question regarding the quality of these tests has not been considered so far. For this purpose, we propose in this paper a novel quality-driven methodology based on mutation analysis. By elevating the main concepts of mutation-based qualification to the context of SDV, our methodology is capable to detect serious quality issues in the SW tests. At its heart is a novel consistency analysis, that measures the coverage of the IP in HW/SW co-simulation in a lightweight fashion and relates this coverage to the SW test results to provide clear feedback on how to further improve the quality of tests. We provide two case studies on real-world VPs and SW tests to demonstrate the applicability and efficacy of our methodology.","PeriodicalId":297899,"journal":{"name":"2016 IEEE 34th International Conference on Computer Design (ICCD)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133851282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Shuffling across rounds: A lightweight strategy to counter side-channel attacks 跨回合洗牌:对抗侧通道攻击的轻量级策略

2016 IEEE 34th International Conference on Computer Design (ICCD) Pub Date : 2016-10-01 DOI: 10.1109/ICCD.2016.7753323

Sikhar Patranabis, Debapriya Basu Roy, Praveen Kumar Vadnala, Debdeep Mukhopadhyay, Santosh K. Ghosh

{"title":"Shuffling across rounds: A lightweight strategy to counter side-channel attacks","authors":"Sikhar Patranabis, Debapriya Basu Roy, Praveen Kumar Vadnala, Debdeep Mukhopadhyay, Santosh K. Ghosh","doi":"10.1109/ICCD.2016.7753323","DOIUrl":"https://doi.org/10.1109/ICCD.2016.7753323","url":null,"abstract":"Side-channel attacks are a potent threat to the security of devices implementing cryptographic algorithms. Designing lightweight countermeasures against side-channel analysis that can run on resource constrained devices is a major challenge. One such lightweight countermeasure is shuffling, in which the designer randomly permutes the order of execution of potentially vulnerable operations. State of the art shuffling countermeasures advocate shuffling a set of independent operations in a single round of a cryptographic algorithm, but are often found to be insufficient as standalone countermeasures. In this paper, we propose a two-round version of the shuffling countermeasure, and test its security when applied to a serialized implementation of AES-128 using Test Vector Leakage Assessment (TVLA). Our results show that the required number of traces to break AES-128 implemented using our proposed countermeasure is significantly larger than the implementations using simple one-round shuffling. Furthermore, the new shuffling method has significantly lower overhead of around 1.3 times, as compared to other side-channel countermeasures such as masking that have an overhead of approximately two times.","PeriodicalId":297899,"journal":{"name":"2016 IEEE 34th International Conference on Computer Design (ICCD)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123644105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

×86 computer architecture simulators: A comparative study ×86计算机体系结构模拟器:比较研究

2016 IEEE 34th International Conference on Computer Design (ICCD) Pub Date : 2016-10-01 DOI: 10.1109/ICCD.2016.7753351

Ayaz Akram, L. Sawalha

引用次数: 24

Isolation-based decorrelation of stochastic circuits 基于隔离的随机电路去相关

2016 IEEE 34th International Conference on Computer Design (ICCD) Pub Date : 2016-10-01 DOI: 10.1109/ICCD.2016.7753265

Pai-Shun Ting, J. Hayes

{"title":"Isolation-based decorrelation of stochastic circuits","authors":"Pai-Shun Ting, J. Hayes","doi":"10.1109/ICCD.2016.7753265","DOIUrl":"https://doi.org/10.1109/ICCD.2016.7753265","url":null,"abstract":"Stochastic computing (SC) performs arithmetic on randomized bit-streams called stochastic numbers (SNs) using standard logic circuits. SC has many appealing features such as error tolerance, low power, and low area cost. However, it suffers from severe accuracy loss due to correlation or insufficient randomness. SNs can be decorrelated by regenerating them from independent random sources. This is the preferred decorrelation method mentioned in the literature, but it often entails huge area and delay overhead. An attractive alternative is isolation-based decorrelation, which is the focus of this research. Isolation works by inserting delays (isolators) into a stochastic circuit to eliminate undesirable interactions among its SNs. Surprisingly, although it has far lower cost than regeneration, isolation has not been studied systematically before, hindering its practical use. The paper first examines the basic characteristics of SC isolation. We show that unless carefully used, it can result in excessive isolator numbers or unexpectedly corrupt a circuit's function. We therefore formally characterize the behavior of an isolation-decorrelated circuit, and derive conditions for correct deployment of isolators. We then describe the first isolator placement algorithm designed to minimize the number of isolators. Finally, we present supporting data obtained from simulation experiments on representative circuits.","PeriodicalId":297899,"journal":{"name":"2016 IEEE 34th International Conference on Computer Design (ICCD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129426844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 35