发布求助
文献互助 智能选刊 最新文献

DAC Design Automation Conference 2012最新文献

筛选
英文 中文
Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI 在45nm SOI中使用16节点芯片原型接近网状NoC的理论极限
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228431
Sunghyun Park, T. Krishna, C. Chen, Bhavya K. Daya, A. Chandrakasan, L. Peh
{"title":"Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI","authors":"Sunghyun Park, T. Krishna, C. Chen, Bhavya K. Daya, A. Chandrakasan, L. Peh","doi":"10.1145/2228360.2228431","DOIUrl":"https://doi.org/10.1145/2228360.2228431","url":null,"abstract":"In this paper, we present a case study of our chip prototype of a 16-node 4×4 mesh NoC fabricated in 45nm SOI CMOS that aims to simultaneously optimize energy-latency-throughput for unicasts, multicasts and broadcasts. We first define and analyze the theoretical limits of a mesh NoC in latency, throughput and energy, then describe how we approach these limits through a combination of microarchitecture and circuit techniques. Our 1.1V 1GHz NoC chip achieves 1-cycle router-and-link latency at each hop and energy-efficient router-level multicast support, delivering 892Gb/s (87.1% of the theoretical bandwidth limit) at 531.4mW for a mixed traffic of unicasts and broadcasts. Through this fabrication, we derive insights that help guide our research, and we believe, will also be useful to the NoC and multicore research community.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114777346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 107
Metronome: Operating system level performance management via self-adaptive computing Metronome:通过自适应计算进行操作系统级性能管理
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228514
F. Sironi, D. Bartolini, Simone Campanoni, F. Cancare, H. Hoffmann, D. Sciuto, M. Santambrogio
{"title":"Metronome: Operating system level performance management via self-adaptive computing","authors":"F. Sironi, D. Bartolini, Simone Campanoni, F. Cancare, H. Hoffmann, D. Sciuto, M. Santambrogio","doi":"10.1145/2228360.2228514","DOIUrl":"https://doi.org/10.1145/2228360.2228514","url":null,"abstract":"In this paper, we present Metronome: a framework to enhance commodity operating systems with self-adaptive capabilities. The Metronome framework features two distinct components: Heart Rate Monitor (HRM) and Performance - Aware Fair Scheduler (PAFS). HRM is an active monitoring infrastructure implementing the observe phase of a self - adaptive computing system Observe - Decide - Act (ODA) control loop, while PAFS is an adaptation policy implementing the decide and act phases of the control loop. Metronome was designed and developed looking towards multi - core processors; therefore, its experimental evaluation has been carried on with the PARSEC 2.1 benchmark suite.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127604620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
A code morphing methodology to automate power analysis countermeasures 一种自动功率分析对策的代码变形方法
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228376
G. Agosta, Alessandro Barenghi, Gerardo Pelosi
{"title":"A code morphing methodology to automate power analysis countermeasures","authors":"G. Agosta, Alessandro Barenghi, Gerardo Pelosi","doi":"10.1145/2228360.2228376","DOIUrl":"https://doi.org/10.1145/2228360.2228376","url":null,"abstract":"We introduce a general framework to automate the application of countermeasures against Differential Power Attacks aimed at software implementations of cryptographic primitives. The approach enables the generation of multiple versions of the code, to prevent an attacker from recognizing the exact point in time where the observed operation is executed and how such operation is performed. The strategy increases the effort needed to retrieve the secret key through hindering the formulation of a correct hypothetical consumption to be correlated with the power measurements. The experimental evaluation shows how a DPA attack against OpenSSL AES implementation on an industrial grade ARM-based SoC is hindered with limited performance overhead.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"35 14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131479891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 73
Physics matters: Statistical aging prediction under trapping/detrapping 物理问题:捕获/去捕获下的统计老化预测
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228388
J. Velamala, K. Sutaria, Takashi Sato, Yu Cao
{"title":"Physics matters: Statistical aging prediction under trapping/detrapping","authors":"J. Velamala, K. Sutaria, Takashi Sato, Yu Cao","doi":"10.1145/2228360.2228388","DOIUrl":"https://doi.org/10.1145/2228360.2228388","url":null,"abstract":"Randomness in Negative Bias Temperature Instability (NBTI) process poses a dramatic challenge on reliability prediction of digital circuits. Accurate statistical aging prediction is essential in order to develop robust guard banding and protection strategies during the design stage. Variations in device level and supply voltage due to Dynamic Voltage Scaling (DVS) need to be considered in aging analysis. The statistical device data collected from 65nm test chip shows that degradation behavior derived from trapping/detrapping mechanism is accurate under statistical variations compared to conventional Reaction Diffusion (RD) theory. The unique features of this work include (1) Aging model development as a function of technology parameters based on trapping/detrapping theory (2) Reliability prediction under device variations and DVS with solid validation with using 65nm statistical silicon data (3) Asymmetric aged timing analysis under NBTI and comprehensive evaluation of our framework in ISCAS89 sequential circuits. Further, we show that RD based NBTI model significantly overestimates the degradation and TD model correctly captures aging variability. These results provide design insights under statistical NBTI aging and enhance the prediction efficiency.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128932123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors 基于STT-MRAM的嵌入式处理器高速缓存构建
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228521
Lei Jiang, Bo Zhao, Youtao Zhang, Jun Yang
{"title":"Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors","authors":"Lei Jiang, Bo Zhao, Youtao Zhang, Jun Yang","doi":"10.1145/2228360.2228521","DOIUrl":"https://doi.org/10.1145/2228360.2228521","url":null,"abstract":"MLC STT-MRAM (Multi-level Cell Spin-Transfer Torque Magnetic RAM), an emerging non-volatile memory technology, has become a promising candidate to construct L2 caches for high-end embedded processors. However, the long write latency limits the effectiveness of MLC STT-MRAM based L2 caches. In this paper, we address this limitation with two novel designs: Line Pairing (LP) and Line Swapping (LS). LP forms fast cachelines by re-organizing MLC soft bits which are faster to write. LS dynamically stores frequently written data into these fast cachelines. Our experimental results show that LP and LS improve system performance by 15% and reduce energy consumption by 21%.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131063586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 77
Alternate hammering test for application-specific DRAMs and an industrial case study 针对特定应用的dram的替代锤击测试和工业案例研究
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228543
Rei-Fu Huang, Hao-Yu Yang, M. Chao, Shih-Chin Lin
{"title":"Alternate hammering test for application-specific DRAMs and an industrial case study","authors":"Rei-Fu Huang, Hao-Yu Yang, M. Chao, Shih-Chin Lin","doi":"10.1145/2228360.2228543","DOIUrl":"https://doi.org/10.1145/2228360.2228543","url":null,"abstract":"This paper presents a novel memory test algorithm, named alternate hammering test, to detect the pairwise word-line hammering faults for application-specific DRAMs. Unlike previous hammering tests, which require excessively long test time, the alternate hammering test is designed scalable to industrial DRAM arrays by considering the array layout for potential fault sites and the highest DRAM-access frequency in real system applications. The effectiveness and efficiency of the proposed alternate hammering test are validated through the test application to an eDRAM macro embedded in a storage-application SoC.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114935221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
An information-theoretic framework for optimal temperature sensor allocation and full-chip thermal monitoring 温度传感器优化配置与全芯片热监测的信息论框架
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228476
Huapeng Zhou, Xin Li, Chen-Yong Cher, E. Kursun, Haifeng Qian, S. Yao
{"title":"An information-theoretic framework for optimal temperature sensor allocation and full-chip thermal monitoring","authors":"Huapeng Zhou, Xin Li, Chen-Yong Cher, E. Kursun, Haifeng Qian, S. Yao","doi":"10.1145/2228360.2228476","DOIUrl":"https://doi.org/10.1145/2228360.2228476","url":null,"abstract":"Full-chip thermal monitoring is an important and challenging issue in today's microprocessor design. In this paper, we propose a new information-theoretic framework to quantitatively model the uncertainty of on-chip temperature variation by differential entropy. Based on this framework, an efficient optimization scheme is developed to find the optimal spatial locations for temperature sensors such that the full-chip thermal map can be accurately captured with a minimum number of on-chip sensors. In addition, several efficient numerical algorithms are proposed to minimize the computational cost of the proposed entropy calculation and optimization. As will be demonstrated by our experimental examples, the proposed entropy-based method achieves superior accuracy (1.4× error reduction) for full-chip thermal monitoring over prior art.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117258547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Exploiting spatiotemporal and device contexts for energy-efficient mobile embedded systems 开发节能移动嵌入式系统的时空和设备环境
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228599
Brad K. Donohoo, Chris Ohlsen, S. Pasricha, Charles W. Anderson
{"title":"Exploiting spatiotemporal and device contexts for energy-efficient mobile embedded systems","authors":"Brad K. Donohoo, Chris Ohlsen, S. Pasricha, Charles W. Anderson","doi":"10.1145/2228360.2228599","DOIUrl":"https://doi.org/10.1145/2228360.2228599","url":null,"abstract":"Within the past decade, mobile computing has morphed into a principal form of human communication, business, and social interaction. Unfortunately, the energy demands of newer ambient intelligence and collaborative technologies on mobile devices have greatly overwhelmed modern energy storage abilities. This paper proposes several novel techniques that exploit spatiotemporal and device context to predict device interface configurations that can optimize energy consumption in mobile embedded systems. These techniques, which include variants of linear discriminant analysis, linear logistic regression, non-linear logistic regression with neural networks, and k-nearest neighbor are explored and compared on synthetic and user traces from real-world usage studies. The experimental results show that up to 90% successful prediction is possible with neural networks and k-nearest neighbor algorithms, improving upon prediction strategies in prior work by approximately 50%. Further, an average improvement of 24% energy savings is achieved compared to state-of-the-art prior work on energy-efficient location-sensing.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116328439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
AMOR: An efficient aggregating based model order reduction method for many-terminal interconnect circuits 多端互连电路中一种有效的基于聚合的模型降阶方法
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228416
Yangfeng Su, Fan Yang, Xuan Zeng
{"title":"AMOR: An efficient aggregating based model order reduction method for many-terminal interconnect circuits","authors":"Yangfeng Su, Fan Yang, Xuan Zeng","doi":"10.1145/2228360.2228416","DOIUrl":"https://doi.org/10.1145/2228360.2228416","url":null,"abstract":"In this paper, we propose an efficient Aggregating based Model Order Reduction method (AMOR) for many-terminal interconnect circuits. The proposed AMOR method is based on the observation that those adjacent nodes of interconnect circuits with almost the same voltage can be aggregated together as a “super node”. Motivated by such an idea, we propose an efficient spectral partition algorithm in AMOR method to partition the nodes into groups with almost the same voltages. The reduced-order models are then obtained by aggregating the adjacent nodes within the same groups together as “super nodes” in AMOR method. The efficiency of AMOR method is not limited by the numbers of the terminals of the networks. Moreover, noticing that the aggregating procedure can be regarded as mapping the original problem into a coarse-grid problem in multigrid method, we propose a computation-efficient smoothing procedure to further improve the simulation accuracy of the reduced-order models. With such a strategy, the simulation accuracy of the reduced-order models can always be guaranteed. Numerical results have demonstrated that, without the smoothing procedure, the reduced-order models obtained by AMOR can still achieve higher simulation efficiency in terms of accuracy and CPU time than the reduced-order models obtained by the existing elimination based methods. With the smoothing procedure, the simulation accuracy of the reduced-order models can further be improved with several iterations.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122109930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Standard cell routing via Boolean satisfiability 通过布尔可满足性的标准单元路由
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228470
N. Ryzhenko, S. Burns
{"title":"Standard cell routing via Boolean satisfiability","authors":"N. Ryzhenko, S. Burns","doi":"10.1145/2228360.2228470","DOIUrl":"https://doi.org/10.1145/2228360.2228470","url":null,"abstract":"We propose a flow for routing nets within a standard cell that 1) generates candidate routes for point-to-point segments; 2) finds conflicts (electrical shorts and geometric design rule violations) between candidate routes; and 3) solves a SAT instance producing a legal and complete routing for all nets in the standard cell. This approach enables routing automation for cutting-edge process technology nodes. We present how to make this technique more effective by introducing pruning techniques to reduce the work required in all three steps. We also show how we can further optimize routing quality within the SAT formulation through the use of successively more stringent constraints. Recent improvements in the speed of SAT solvers make such a formulation practical for even complex standard cells. A routing tool based on our SAT formulation is currently being used to route real industrial standard cell layouts. It demonstrates acceptable runtime and 89% coverage of our industrial standard cell library, including scan flip-flops, adders, and multiplexers. We also observe a significant reduction in amount of metal 2 routing in comparison with industrial hand-crafted standard cells.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124082326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信