Yan Li, Seungpil Lee, K. Oowada, Hao Nguyen, Q. Nguyen, Nima Mokhlesi, Cynthia Hsu, Jason Li, Venky Ramachandra, T. Kamei, M. Higashitani, T. Pham, M. Honma, Y. Watanabe, K. Ino, Binh Le, Byungki Woo, Khin Htoo, Taiyuan Tseng, Long Pham, F. Tsai, Kwang-Ho Kim, Yi-Chieh Chen, Min She, Jonghak Yuh, A. Chu, Cheng Chen, R. Puri, Hung-Szu Lin, Yi-Fang Chen, William Mak, Jonathan Huynh, J. Chan, Mitsuyuki Watanabe, Dan Yang, Grishma Shah, Pavithra Souriraj, Dinesh Tadepalli, T. Suman, Ray Gao, Viski Popuri, Behdad Azarbayjani, Ravindra Madpur, J. Lan, E. Yero, Feng Pan, Patrick Hong, Jang Yong Kang, F. Moogat, Y. Fong, R. Cernea, S. Huynh, Cuong Trinh, M. Mofidi, Ritu Shrivastava, K. Quader
{"title":"128Gb 3b/cell NAND flash memory in 19nm technology with 18MB/s write rate and 400Mb/s toggle mode","authors":"Yan Li, Seungpil Lee, K. Oowada, Hao Nguyen, Q. Nguyen, Nima Mokhlesi, Cynthia Hsu, Jason Li, Venky Ramachandra, T. Kamei, M. Higashitani, T. Pham, M. Honma, Y. Watanabe, K. Ino, Binh Le, Byungki Woo, Khin Htoo, Taiyuan Tseng, Long Pham, F. Tsai, Kwang-Ho Kim, Yi-Chieh Chen, Min She, Jonghak Yuh, A. Chu, Cheng Chen, R. Puri, Hung-Szu Lin, Yi-Fang Chen, William Mak, Jonathan Huynh, J. Chan, Mitsuyuki Watanabe, Dan Yang, Grishma Shah, Pavithra Souriraj, Dinesh Tadepalli, T. Suman, Ray Gao, Viski Popuri, Behdad Azarbayjani, Ravindra Madpur, J. Lan, E. Yero, Feng Pan, Patrick Hong, Jang Yong Kang, F. Moogat, Y. Fong, R. Cernea, S. Huynh, Cuong Trinh, M. Mofidi, Ritu Shrivastava, K. Quader","doi":"10.1109/ISSCC.2012.6177080","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177080","url":null,"abstract":"This paper addresses challenges with improvements made over previous NAND generations to achieve high performance while maintaining a low fail-bit count (FBC) and cost savings from an improved architecture and tightly packed peripheral circuits. Air gap [2,3] technology further improves write throughput by reducing neighbor interference and WL RC. A toggle mode 400Mb/s I/O interface reduces system overhead and enhances overall performance.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134638675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 0.5V 4.95μW 11.8fps PWM CMOS imager with 82dB dynamic range and 0.055% fixed-pattern noise","authors":"Meng-Ting Chung, C. Hsieh","doi":"10.1109/ISSCC.2012.6176942","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176942","url":null,"abstract":"In this paper, a 0.5V 64×40-pixel PWM imager is prototyped in standard 0.18μm CMOS. A threshold-variation-cancelling (TVC) scheme is developed to solve the non-uniformity issue of in-pixel comparators, which results in 0.055% fixed-pattern noise (FPN). To deal with the limited signal swing at 0.5V operation, a programmable current-controlled threshold (PCCT) scheme is implemented to achieve a 56.5dB boost in dynamic range.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133282776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sunwoo Kwon, Injeong Kim, Shinyoung Yi, S. Kang, Sangheon Lee, T. Hwang, Byoungkwon Moon, Yunyoung Choi, Hosung Sung, Jinseok Koh
{"title":"A 0.028% THD+N, 91% power-efficiency, 3-level PWM Class-D amplifier with a true differential front-end","authors":"Sunwoo Kwon, Injeong Kim, Shinyoung Yi, S. Kang, Sangheon Lee, T. Hwang, Byoungkwon Moon, Yunyoung Choi, Hosung Sung, Jinseok Koh","doi":"10.1109/ISSCC.2012.6176891","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176891","url":null,"abstract":"A Class-D amplifier (CDA) is best suitable for audio mobile applications due to its high-power efficiency, thus enabling to remove a bulky heat sink. A traditional Class-D amplifier uses a 2-level output switching scheme. There typically exist an external LC filter and a bulky capacitor to block a DC average current and to protect the speaker from the current, which increases the bill of materials. As a remedy, a 3-level switching scheme allows to eliminate the filters, hence helping to reduce the system cost. Moreover, the 3-level switching scheme provides additional benefits of less electromagnetic interference and better power efficiency. The 3-level approach prevails with the help of various modulation techniques such as a pulse-width modulation (PWM) [1,2], a sliding-mode control [3], and a uniform PWM [4] method.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122263971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hangue Park, B. Gosselin, M. Kiani, Hyung-Min Lee, Jeonghee Kim, Xueliang Huo, Maysam Ghovanloo
{"title":"A wireless magnetoresistive sensing system for an intra-oral tongue-computer interface","authors":"Hangue Park, B. Gosselin, M. Kiani, Hyung-Min Lee, Jeonghee Kim, Xueliang Huo, Maysam Ghovanloo","doi":"10.1109/ISSCC.2012.6176947","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176947","url":null,"abstract":"The Tongue Drive System (TDS) is a new minimally invasive, unobtrusive, wireless, and wearable tongue-operated assistive technology (AT) that enables individuals with severe physical disabilities to control environments with their free tongue motion. An array of magnetic sensors wirelessly tracks the position of a magnetic tracer attached to the tongue via adhesives or piercing, and a sensor signal-processing (SSP) algorithm converts a set of tongue gestures to user-defined commands in real time [1]. In the external TDS (eTDS), which is undergoing clinical trials, electronics are embedded in a customized headset, which supports the sensors on a pair of bilateral extensions near the cheeks [2]. Considering the importance of such ATs in users' daily lives, the mechanical stability of the eTDS on the head is a concern. In this paper we report an intraoral TDS (iTDS) that reliably fits inside a user's mouth in the form of a dental retainer to be well protected within the oral cavity.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130271534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Bol, J. Vos, Cédric Hocquet, F. Botman, François Durvaux, S. Boyd, D. Flandre, J. Legat
{"title":"A 25MHz 7μW/MHz ultra-low-voltage microcontroller SoC in 65nm LP/GP CMOS for low-carbon wireless sensor nodes","authors":"D. Bol, J. Vos, Cédric Hocquet, F. Botman, François Durvaux, S. Boyd, D. Flandre, J. Legat","doi":"10.1109/ISSCC.2012.6177104","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177104","url":null,"abstract":"The vision of the Internet of Things with ambient intelligence calls for the deployment of up to a trillion connected wireless sensor nodes (WSNs). Minimizing the carbon footprint of each node is paramount from the sustainability perspective. In ultra-low-power applications, the life-cycle carbon footprint results from a complex balance between both embodied and use-phase energies [1]. The embodied energy arises mainly from CMOS chip manufacturing, and is essentially proportional to die area. Use-phase energy depends on both active and sleep-mode power, because of long stand-by periods in WSNs. In this paper, we present an ultra-low-power 25MHz microcontroller SoC that fully exploits the versatility of a 65nm CMOS process with a low-power/general-purpose (LP/GP) transistor mix (dual-core oxide) to obtain: i) 7μW/MHz active power consumption due to a 0.4V ultra-low-voltage (ULV) thin-core-oxide (GP) CPU supplied by a 78%-efficiency embedded DC/DC converter; ii) 0.66mm2 die area for low embodied energy due to a compact converter design and a dual-VDD architecture, enabling the use of the foundry's 1V high-density 6T SRAM bitcell; and, iii) 1.5μW sleep-mode power due to body-biased sleep transistors embedded into the converter and thick-core-oxide (LP) MOSFETs for retentive SRAM and always-on peripherals (AOP). Moreover, an on-chip adaptive voltage scaling (AVS) system controlling the converter ensures safe 25MHz operation at ULV for all PVT conditions. A multi-Vt clock tree is also proposed to achieve reliable timing closure with low-power SoC features. Finally, a glitch-masking instruction cache (I$) is implemented to reduce the access power of the 1V program memory (PMEM).","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127723831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 6.7-to-9.2GHz 55nm CMOS hybrid Class-B/Class-C cellular TX VCO","authors":"Luca Fanori, A. Liscidini, P. Andreani","doi":"10.1109/ISSCC.2012.6177049","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177049","url":null,"abstract":"The design of very-wide-band CMOS voltage-controlled oscillators (VCOs) compliant with the phase-noise specifications of cellular transmitters is non-trivial, especially considering the GSM standard, where the phase noise exhibited by the local oscillator (LO, generated by the cascade of VCO, buffers, and usually frequency dividers) should be several dB below -162dBc/Hz at 20MHz frequency offset from the carrier. As shown in [1], challenging phase-noise requirements can embrace the WCDMA transmitter as well (e.g. -166dBc/Hz at 45MHz frequency offset for WCDMA band VIII), if cheap antenna duplexers are chosen to minimize costs. In such scenarios, and particularly in the very relevant case of WCDMA transmitting at moderate power levels, the LO power efficiency is still one of the limiting factors for a long-lasting battery life, motivating the ongoing quest for VCO power optimization.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117020169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A TDC-less ADPLL with 200-to-3200MHz range and 3mW power dissipation for mobile SoC clocking in 22nm CMOS","authors":"N. August, Hyung-Jin Lee, M. Vandepas, R. Parker","doi":"10.1109/ISSCC.2012.6176995","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176995","url":null,"abstract":"Mobile SoC designs demand a low-power clocking system to maximize battery life. The host PLL is critical since it must remain enabled to support always-on, always-connected operation. In addition, the host PLL should offer wide frequency range, low area, flexible bandwidth, scalability to future manufacturing processes, negligible lock time compared to the power-state-cycling time, and acceptable period jitter for clocking digital logic.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121147968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Tang, G. Virbila, D. Murphy, F. Hsiao, Yen-Hsiang Wang, Q. Gu, Zhiwei Xu, Y. Wu, M. Zhu, Mau-Chung Frank Chang
{"title":"A 144GHz 0.76cm-resolution sub-carrier SAR phase radar for 3D imaging in 65nm CMOS","authors":"A. Tang, G. Virbila, D. Murphy, F. Hsiao, Yen-Hsiang Wang, Q. Gu, Zhiwei Xu, Y. Wu, M. Zhu, Mau-Chung Frank Chang","doi":"10.1109/ISSCC.2012.6177009","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177009","url":null,"abstract":"Millimeter-Wave-based radar has gained attention in recent years for automotive and object detection applications. Several new applications are also emerging which employ mm-Wave radar techniques to construct short range mm-Wave 3D imaging systems for security screening and biomedical applications. At present, these types of 3D mm-Wave imagers have only been demonstrated in lll-V technology, as CMOS-based radar suffers several range and resolution limitations due to limited output power and linearity.Most CMOS mm-Wave radar systems used in automotive applications are based on Frequency-Modulated Continuous-Wave (FMCW) ranging techniques in which the carrier is swept to produce a frequency offset at the receiver output proportional to the round-trip distance between the radar and target. While FMCW is an excellent approach for accurate ranging, its implementation becomes particularly difficult at high frequencies as the resolution is heavily dependent on sweep linearity and the high RF front-end performance required to support the wideband swept carrier. For 3D mm-Wave imaging applications, this high operating frequency is indispensable as the attainable spatial (XY) resolution is fundamentally limited by the wavelength of the imaging system. Higher frequency also helps relax focusing lens requirements, as the optical diffraction limit is set by the ratio of the radar wavelength over the lens aperture size.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121501715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers","authors":"Youngjoo Lee, Hoyoung Yoo, Injae Yoo, I. Park","doi":"10.1109/ISSCC.2012.6177075","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177075","url":null,"abstract":"Solid-state drives (SSDs), built with many flash memory channels, is usually connected to the host through an advanced high-speed serial interface such as SATA III associated with a transfer rate of 6Gb/s [1-2]. However, the performance of SSD is in general determined by the throughput of the ECC blocks necessary to overcome the high error-rate [3]. The binary BCH code is widely used for the SSD due to its powerful error-correction capability. As it is hard to achieve high-throughput strong BCH decoders [4-5], multiple BCH decoders are typically on a high-performance SSD controller, leading to a significant increase of hardware complexity. This paper presents an efficient BCH encoder/decoder architecture achieving a decoding throughput of 6Gb/s. The overall architecture shown in Fig. 25.3.1 includes a single BCH decoder and a multi-threaded BCH encoder. The single BCH encoder is responsible for all the channels and services a channel at a time in a round-robin manner.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117157464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Matthew R. Fojtik, D. Fick, Yejoong Kim, N. Pinckney, D. Harris, D. Blaauw, D. Sylvester
{"title":"Bubble Razor: An architecture-independent approach to timing-error detection and correction","authors":"Matthew R. Fojtik, D. Fick, Yejoong Kim, N. Pinckney, D. Harris, D. Blaauw, D. Sylvester","doi":"10.1109/ISSCC.2012.6177103","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177103","url":null,"abstract":"Several methods that eliminate timing margins by detecting and correcting transient delay errors have been proposed. These Razor-style systems replace critical flip-flops with ones that detect late arriving signals, and use architectural replay to correct errors. However, none of these methods have been applied to a complete commercial processor due to their architectural invasiveness. In addition, these Razor techniques introduce significant hold time constraints that are difficult to meet given worsening timing variability. To address these two issues we propose Bubble Razor (B-Razor), which uses a novel error-detection technique based on two-phase latch timing and a local replay mechanism that can be inserted automatically in any design. The error detec tion technique breaks the dependency between minimum delay and speculation window, restoring hold-time constraints to conventional values and allowing timing speculation of up to 100% of nominal delay. The large timing specula tion makes Bubble Razor especially applicable to low-voltage designs where tim ing variation grows exponentially.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131515493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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