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2012 IEEE International Solid-State Circuits Conference最新文献

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A 14.2mW 2.55-to-3GHz cascaded PLL with reference injection, 800MHz delta-sigma modulator and 255fsrms integrated jitter in 0.13μm CMOS 一个14.2mW 2.55- 3ghz级联锁相环，参考注入，800MHz δ - σ调制器和255fsrms集成抖动在0.13μm CMOS
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6177038
Dongmin Park, Seonghwan Cho
{"title":"A 14.2mW 2.55-to-3GHz cascaded PLL with reference injection, 800MHz delta-sigma modulator and 255fsrms integrated jitter in 0.13μm CMOS","authors":"Dongmin Park, Seonghwan Cho","doi":"10.1109/ISSCC.2012.6177038","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177038","url":null,"abstract":"Fractional-N PLLs [1-3] are widely used due to their fine frequency resolution. However, their phase noise performance is typically worse than the integer-N [4, 5, 6] counterpart due to the quantization noise of the delta-sigma modulator (DSM). In this paper, we propose a low-noise fractional-N PLL that achieves best-case figure-of-merit (FOM) of -240.3dB, rms jitter of 255fsrms and worst-case fractional spur of -53.9dBc by using an 800MHz reference generated from a low-noise reference-injected integer-N PLL.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122189701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A capacitively coupled chopper instrumentation amplifier with a ±30V common-mode range, 160dB CMRR and 5μV offset 电容耦合斩波仪表放大器，共模范围为±30V, CMRR为160dB，偏移量为5μV
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6177045
Qinwen Fan, J. Huijsing, K. Makinwa
{"title":"A capacitively coupled chopper instrumentation amplifier with a ±30V common-mode range, 160dB CMRR and 5μV offset","authors":"Qinwen Fan, J. Huijsing, K. Makinwa","doi":"10.1109/ISSCC.2012.6177045","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177045","url":null,"abstract":"This paper describes a capacitively coupled chopper instrumentation amplifier (CCIA) for current-sensing applications. A capacitively driven input chopper enables a ±30V input common-mode (CM) range and an input offset less than 5μV. The CCIA does not draw supply current from its input terminals or require a separate high-voltage (HV) supply; and has a common-mode rejection ratio (CMRR) in excess of 160dB, both of which represent significant improvements on the state-of-the-art [1-3]. Implemented in a HV CMOS 0.7μm technology, the CCIA achieves an NEF of 6.1 (6.5× better than [1-3]), while drawing only 26μA from a 3V supply.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131297072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
A sampling-based 128×128 direct photon-counting X-ray image sensor with 3 energy bins and spatial resolution of 60μm/pixel 一种基于采样的128×128直接光子计数x射线图像传感器，具有3个能量仓，空间分辨率为60μm/pixel
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6176941
Hyunsik Kim, Sang-Wook Han, Junhyeok Yang, Sung-il Kim, Young Kim, Sangwook Kim, D. Yoon, Jun Su Lee, Jae-Chul Park, Y. Sung, Seong-Deok Lee, S. Ryu, G. Cho
{"title":"A sampling-based 128×128 direct photon-counting X-ray image sensor with 3 energy bins and spatial resolution of 60μm/pixel","authors":"Hyunsik Kim, Sang-Wook Han, Junhyeok Yang, Sung-il Kim, Young Kim, Sangwook Kim, D. Yoon, Jun Su Lee, Jae-Chul Park, Y. Sung, Seong-Deok Lee, S. Ryu, G. Cho","doi":"10.1109/ISSCC.2012.6176941","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176941","url":null,"abstract":"The photon-counting method is one of several useful image-detection methods for digital X-ray imaging. The direct-type photon-counting method has higher X-ray-to-charge conversion efficiency and position resolution compared with the indirect-type detection method. Therefore, direct-type detection is more suitable for medical imaging applications for which the dose efficiency and the image quality are especially important.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121109028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A high-voltage CMOS IC and embedded system for distributed photovoltaic energy optimization with over 99% effective conversion efficiency and insertion loss below 0.1% 一种用于分布式光伏能源优化的高压CMOS集成电路及嵌入式系统，有效转换效率超过99%，插入损耗低于0.1%
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6176893
J. Stauth, M. Seeman, K. Kesarwani
{"title":"A high-voltage CMOS IC and embedded system for distributed photovoltaic energy optimization with over 99% effective conversion efficiency and insertion loss below 0.1%","authors":"J. Stauth, M. Seeman, K. Kesarwani","doi":"10.1109/ISSCC.2012.6176893","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176893","url":null,"abstract":"Solar photovoltaic (PV) energy has increased in importance in recent years as a viable alternative to carbon-producing sources of energy. In an effort to drive PV energy towards grid parity, there is a need to improve the power electronics and architecture for grid-connected systems. Traditional PV systems use a central inverter to manage multiple strings of series-connected PV modules. With mismatch among the PV cells, the energy production of the array suffers in several ways: 1) in series strings, current is limited to the lowest-performing cell in the string, 2) if current is forced to exceed this level, external bypass diodes need to turn on throwing away power available in the string and incurring conductive losses, 3) with bypass diodes on, total string voltage may deviate from maximum power voltage (Vmpp), reducing energy production of all modules in the string.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127098028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
A ±0.4°C (3σ) −70 to 200°C time-domain temperature sensor based on heat diffusion in Si and SiO2 ±0.4°C (3σ)−70 ~ 200°C的Si和SiO2热扩散时域温度传感器
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6176976
Caspar P. L. van Vroonhoven, D. d'Aquino, K. Makinwa
{"title":"A ±0.4°C (3σ) −70 to 200°C time-domain temperature sensor based on heat diffusion in Si and SiO2","authors":"Caspar P. L. van Vroonhoven, D. d'Aquino, K. Makinwa","doi":"10.1109/ISSCC.2012.6176976","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176976","url":null,"abstract":"Despite the increasing use of ICs at very high temperatures (>;150°C) in automotive and industrial applications, sensing such temperatures is still mostly done with discrete thermocouples or thermistors. This is because conventional integrated temperature sensors are based on BJTs, which have a strongly process-, stress- and temperature-dependent saturation current (Is). Together with other leakage currents, this leads to rapidly increasing temperature errors at high temperatures: up to ±3.0°C at 200°C [1].","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133787761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Optical PCB interconnects, Niche or mainstream? 光PCB互连，利基还是主流?
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6177111
I. Fujimori, Seonghwan Cho, J. Friedrich, J. Stonick
{"title":"Optical PCB interconnects, Niche or mainstream?","authors":"I. Fujimori, Seonghwan Cho, J. Friedrich, J. Stonick","doi":"10.1109/ISSCC.2012.6177111","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177111","url":null,"abstract":"Summary form only given. The continued scaling of information processing systems-on-a-chip using modern technology have made conventional electrical interconnects using copper the bottleneck for data traffic in many applications. Efforts in the area of optical backplane and technology have been underway for several years, generating significant interest due to its potential benefits in power, density and speed. Recently, these efforts have led to discussions regarding the role of embedded optics for chip to chip communication on printed circuit boards. Most signficantly, the advancement in silicon photonics compatible to CMOS technology have accelerated this discussion. A consensus appears to be emerging that PCB interconnects for mainframes and high-end servers will leverage optical technologies, but will these approaches ever go mainstream?","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131218075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A true multistandard, programmable, low-power, full HD video-codec engine for smartphone SoC 一个真正的多标准，可编程，低功耗，全高清视频编解码器引擎的智能手机SoC
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6176986
M. Mehendale, Subrangshu Das, Mohit Sharma, Mihir Mody, R. Reddy, Joseph Meehan, Hideo Tamama, B. Carlson, M. Polley
{"title":"A true multistandard, programmable, low-power, full HD video-codec engine for smartphone SoC","authors":"M. Mehendale, Subrangshu Das, Mohit Sharma, Mihir Mody, R. Reddy, Joseph Meehan, Hideo Tamama, B. Carlson, M. Polley","doi":"10.1109/ISSCC.2012.6176986","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176986","url":null,"abstract":"In this paper, we present IVA-HD, a true multistandard, programmable, full HD video coding engine which adopts optimal hardware-software partitioning to achieve the low-power and area requirements of the OMAP 4 processor. Unlike the approach of using separate IPs for encoder and decoder, IVA-HD uses an integrated codec engine which is area efficient, as most of the decoder logic is reused for the encoder. IVA-HD is architected to perform stream-rate and pixel- rate processing in a single pipeline (that processes one 16x16 macroblock at a time), so as to support the latency requirements of video conferencing.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132568844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth 20nm 1.8V 8Gb PRAM，程序带宽40MB/s
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6176872
Youngdon Choi, I. Song, Mu-Hui Park, Hoeju Chung, Sang-whan Chang, B. Cho, Jinyoung Kim, Younghoon Oh, D. Kwon, Jung Sunwoo, Junho Shin, Yoohwan Rho, Changsoo Lee, M. Kang, Jaeyun Lee, Yongjin Kwon, Soehee Kim, Jaewhan Kim, Yong-jun Lee, Qi Wang, Sooho Cha, Sujin Ahn, H. Horii, Jaewook Lee, KiSeung Kim, Han-Sung Joo, Kwangjin Lee, Yeong-Taek Lee, Jei-Hwan Yoo, G. Jeong
{"title":"A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth","authors":"Youngdon Choi, I. Song, Mu-Hui Park, Hoeju Chung, Sang-whan Chang, B. Cho, Jinyoung Kim, Younghoon Oh, D. Kwon, Jung Sunwoo, Junho Shin, Yoohwan Rho, Changsoo Lee, M. Kang, Jaeyun Lee, Yongjin Kwon, Soehee Kim, Jaewhan Kim, Yong-jun Lee, Qi Wang, Sooho Cha, Sujin Ahn, H. Horii, Jaewook Lee, KiSeung Kim, Han-Sung Joo, Kwangjin Lee, Yeong-Taek Lee, Jei-Hwan Yoo, G. Jeong","doi":"10.1109/ISSCC.2012.6176872","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176872","url":null,"abstract":"Phase-change random access memory (PRAM) is considered as one of the most promising candidates for future memories because of its good scalability and cost-effectiveness [1]. Besides implementations with standard interfaces like NOR flash or LPDDR2-NVM, application-oriented approaches using PRAM as main-memory or storage-class memory have been researched [2-3]. These studies suggest that noticeable merits can be achieved by using PRAM in improving power consumption, system cost, etc. However, relatively low chip density and insufficient write bandwidth of PRAMs are obstacles to better system performance. In this paper, we present an 8Gb PRAM with 40MB/s write bandwidth featuring 8Mb sub-array core architecture with 20nm diode-switched PRAM cells [4]. When an external high voltage is applied, the write bandwidth can be extended as high as 133MB/s.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"13 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113978011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 318
A 5.37mW 10b 200MS/s dual-path pipelined ADC 5.37mW 10b200ms /s双路流水线ADC
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6177091
Yun Chai, Jieh-Tsorng Wu
{"title":"A 5.37mW 10b 200MS/s dual-path pipelined ADC","authors":"Yun Chai, Jieh-Tsorng Wu","doi":"10.1109/ISSCC.2012.6177091","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177091","url":null,"abstract":"The opamps in a switched-capacitor (SC) pipelined ADC provide the functions of sample-and-hold, residue generation, and residue amplification [1,2]. High-performance opamps that meet the requirements for dc gain, speed, and signal range usually consume large power. We propose a scheme where the residue amplification is performed first by a coarse amplifier (CA), and then by a fine amplifier (FA). The CA generates a large-swing output that may not be accurate due to low dc gain and slow speed. Subsequently, the FA produces a small-swing output that stands as the error of the CA. The requirements for the CA and FA are different. They can be designed and optimized separately, resulting in low power dissipation. We report a 10b SC pipelined ADC to demonstrate this technique. Fabricated in 65nm CMOS, this ADC achieves 56.7dB SNDR at 200MS/s sampling rate, and consumes 5.37mW from a 1V supply.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"603 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116327620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias 一个3D系统原型的eDRAM缓存堆叠在类似处理器的逻辑使用硅通孔
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6176968
M. Wordeman, J. Silberman, G. Maier, M. Scheuermann
{"title":"A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias","authors":"M. Wordeman, J. Silberman, G. Maier, M. Scheuermann","doi":"10.1109/ISSCC.2012.6176968","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176968","url":null,"abstract":"3D integration (3DI) holds promise for improved performance of integrated systems by increasing interconnect bandwidth [1]. A processor stacked with cache memory is one potential application of 3DI [2]. This work describes the design and operation of a prototype of a 3D system, constructed by stacking a memory layer, built with eDRAM [3] and logic blocks from the IBM Power7™ processor L3 cache, and a “processor proxy” layer in 45nm CMOS technology [4] enhanced to include through-silicon vias (TSVs) [5]. Unlike the previously reported 3D eDRAM [6], the 3D stack described here is constructed using 50μm pitch μC4's joining the front side of one thick chip to TSV connections on the back side of a thinned chip. TSVs are formed of Cu-filled vias that are ~20μm in diameter and <;100μm deep [5].","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114593509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
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