2012 IEEE International Solid-State Circuits Conference最新文献

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What's next in robots? ∼Sensing, processing, networking toward human brain and body 机器人的下一个发展方向是什么?对人脑和人体的传感、处理、联网
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6177109
K. Arimoto, Sam Kavusi, J. Salisbury
{"title":"What's next in robots? ∼Sensing, processing, networking toward human brain and body","authors":"K. Arimoto, Sam Kavusi, J. Salisbury","doi":"10.1109/ISSCC.2012.6177109","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177109","url":null,"abstract":"Most of us dreamt about robots in our childhood interacting and assisting us in our daily life. They are way beyond fiction and have emerged to become unavoidable in minimally-invasive surgery and industrial automation. There is also an explosion in research areas around autonomous cars, humanoid/android, medical, mobile remote manipulation and personal assistance robots. Such advances largely benefit from to the advances in sensing, signal processing, analog/digital circuits, and devices in semiconductor technologies that are driven by consumer and automotive electronics. Increasingly robotic platforms are also benefiting from the wirelessly connected infrastructure and the cloud computing. Expansion of such applications is going to require more human-friendly and humanlike interactive systems. Improvements in energy efficiency, dependability, security, intelligent sensor networks are among technologies, which are expected from the next generation silicon system, that provide the means to the development of the next generation interactive robots. However, more closed collaboration of the hardware/software design, integration, and data fusion are also must. Robot developers' wish list for the semiconductor industry is endless and their creativ ity is admirable.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130888026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The role of semiconductors in the energy landscape 半导体在能源领域的作用
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6176898
C. Papa
{"title":"The role of semiconductors in the energy landscape","authors":"C. Papa","doi":"10.1109/ISSCC.2012.6176898","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176898","url":null,"abstract":"Semiconductor technologies, products and solutions have long played a key role in improving efficiency along the whole energy chain and the importance of this role will continually increase. The greatest future energy saving will come from the adoption of semiconductor technologies, especially in buildings, which are forecasted to consume around 50% less electricity in 2030. In this area, savings will come from three sources: more efficient appliances (with an estimated 60% reduction), intelligent lighting and HVAC (with up to 50% reduction), and increased energy-consumption consciousness at the consumer level, thanks to energy monitoring in-house systems (with up to 20% potential saving). Furthermore, the advent of the Smart Grid will contribute to energy saving and to eco-sustainability. Grid optimization, through the improved modeling and control that will be possible with the deployment of Smart Meters and Automatic Meter Infrastructures (AMI), will significantly reduce infrastructure losses. Above all, it will enable the integration of renewable sources as alternatives to traditional carbon-based sources, allowing the possibility of meeting international targets such as Europe's EU 20-20-20 target that can strongly contribute reductions in CO2 emissions and containment of global warming.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130677850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On-chip gain reconfigurable 1.2V 24μW chopping instrumentation amplifier with automatic resistor matching in 0.13μm CMOS 片上增益可重构1.2V 24μW斩波仪表放大器,电阻自动匹配0.13μm CMOS
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6177055
F. Michel, M. Steyaert
{"title":"On-chip gain reconfigurable 1.2V 24μW chopping instrumentation amplifier with automatic resistor matching in 0.13μm CMOS","authors":"F. Michel, M. Steyaert","doi":"10.1109/ISSCC.2012.6177055","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177055","url":null,"abstract":"Motivated by low-voltage, low-power and small-size requirements of biomedical and energy scavenging circuits, this work introduces a fully integrated instrumentation amplifier (IA) running at 1.2V with a power consumption of only 24μW. A direct current feedback structure (DCFB) with rail-to-rail output swing is proposed along with a precision reference generation for on-chip resistor trimming. Thus, gain reconfiguration is achieved while guaranteeing low gain error over mismatch, process and temperature variations.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126669368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A 1V 19.3dBm 79GHz power amplifier in 65nm CMOS 一个1V 19.3dBm 79GHz功率放大器在65nm CMOS
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6177001
Kun-Yin Wang, Tao-Yao Chang, Chorng-Kuang Wang
{"title":"A 1V 19.3dBm 79GHz power amplifier in 65nm CMOS","authors":"Kun-Yin Wang, Tao-Yao Chang, Chorng-Kuang Wang","doi":"10.1109/ISSCC.2012.6177001","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177001","url":null,"abstract":"For a highly integrated wireless system including on-chip antennas, high-output- power power amplifiers (PA) are required to cover the desired transmission range. In order to achieve the output power level, power-combining techniques have gained more attention in recent years [1-5]. An efficient power-combining solution is essential since less DC power is needed for the same level of output power, and the difficulties of thermo-dissipation are thus relieved in a high-out- put-power PA. Transformer-based power combining is one of the common tech- niques, which can increase impedance-transformation ratio by increasing the number of input ports and results in a compact layout and reasonable loss [1-3, 5].","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114865863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
A 0.0025mm2 bandgap voltage reference for 1.1V supply in standard 0.16μm CMOS 标准0.16μm CMOS中为1.1V电源提供的0.0025mm2带隙基准电压
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6177053
A. Annema, G. Goksun
{"title":"A 0.0025mm2 bandgap voltage reference for 1.1V supply in standard 0.16μm CMOS","authors":"A. Annema, G. Goksun","doi":"10.1109/ISSCC.2012.6177053","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177053","url":null,"abstract":"Todays ICs usually employ one bandgap voltage reference (BGVR) circuit to generate a well defined voltage that is reused at many places in that IC. The classical BGVR generates a reference voltage that is slightly larger than the material bandgap: a little above 1200mV in silicon. For deep-sub-micron technologies the supply voltage is about the same as the material bandgap which prevents using the classical bandgap structure. As a solution a number of BGVR topologies that create a sub-1V are invented; most of them are based on the structure introduced by Banba [1], some are using resistive voltage division [2] or voltage averaging [3]. For low-power operation high-ohmic resistors (occupying a large area!) must be used in all these techniques, leading to an immediate trade-off between power consumption and chip-area. This trade-off prevents the local generation of reference voltages where they are required: either the power penalty or the area penalty would be too significant. Alternative topologies that do not require high-ohmic resistors typically are not-BGVR-based circuits relying on threshold voltages and hence require trimming to achieve low spread.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114890192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
A 45nm SOI CMOS Class-D mm-Wave PA with >10Vpp differential swing 差分摆幅>10Vpp的45nm SOI CMOS d类毫米波PA
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6176882
I. Sarkas, A. Balteanu, E. Dacquay, A. Tomkins, S. Voinigescu
{"title":"A 45nm SOI CMOS Class-D mm-Wave PA with >10Vpp differential swing","authors":"I. Sarkas, A. Balteanu, E. Dacquay, A. Tomkins, S. Voinigescu","doi":"10.1109/ISSCC.2012.6176882","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176882","url":null,"abstract":"The ever-increasing demand for low-cost portable communication devices pushes for higher integration of wireless transceivers in deeply-scaled silicon technologies. Given the overwhelming digital content of a mobile platform, ideally, the RF components should be realized with topologies that allow for their seamless scaling into 22nm and 14nm CMOS technologies. The Power Amplifier (PA) remains one of the most challenging circuit blocks to implement in nanoscale CMOS due to the strict requirements for output power, efficiency and linearity imposed by wireless communication standards. The low breakdown voltage of nanoscale MOSFETs limits the maximum drain voltage swing and the maximum achievable output power. In order to circumvent this problem, a typical approach is to increase the device size and use a reactive matching network to transform the load resistance to a value significantly lower than 50Ω. Nevertheless, due to the typically low-Q passive components that can be manufactured in a nanoscale CMOS process, and because of the high impedance transformation ratio involved, most of the additional output power that would be gained by increasing the device size is wasted in resistive losses in the matching networks, resulting in poor efficiency. This problem is exacerbated at mm-Wave frequencies where the loss of the passive components is even higher, and using lower fT/fMAX thicker oxide or extended drain MOS devices [1] is not viable.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114915619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
A CMOS impedance cytometer for 3D flowing single-cell real-time analysis with ΔΣ error correction 用于三维流动单细胞实时分析的CMOS阻抗细胞仪,具有ΔΣ误差校正功能
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6177024
Kang-Ho Lee, Jeonghun Nam, Sukhwan Choi, Hyunjung Lim, Sehyun Shin, G. Cho
{"title":"A CMOS impedance cytometer for 3D flowing single-cell real-time analysis with ΔΣ error correction","authors":"Kang-Ho Lee, Jeonghun Nam, Sukhwan Choi, Hyunjung Lim, Sehyun Shin, G. Cho","doi":"10.1109/ISSCC.2012.6177024","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177024","url":null,"abstract":"Flow cytometry is an essential cell analysis technology in clinical immunology and haematology for the diagnosis and prognosis of disease. It involves the counting, identification and sorting of cells [1,2]. Conventional bulk measurements [3] require a large volume of blood, which is not desirable for the early detection of a disease, when only a very small percentage of cells contain evidence of the disease. In this paper, we propose, for the first time, a non-invasive and high-throughput single-cell analysis method using CMOS-integrated circuits in conjunction with a microfluidic channel as the first building block of a complete cell-sorting device.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117014477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A modular 1mm3 die-stacked sensing platform with optical communication and multi-modal energy harvesting 一个模块化的1mm3模堆叠传感平台,具有光通信和多模态能量收集
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6177065
Yoonmyung Lee, Gyouho Kim, S. Bang, Yejoong Kim, Inhee Lee, P. Dutta, D. Sylvester, D. Blaauw
{"title":"A modular 1mm3 die-stacked sensing platform with optical communication and multi-modal energy harvesting","authors":"Yoonmyung Lee, Gyouho Kim, S. Bang, Yejoong Kim, Inhee Lee, P. Dutta, D. Sylvester, D. Blaauw","doi":"10.1109/ISSCC.2012.6177065","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177065","url":null,"abstract":"Wireless sensor nodes have many compelling applications such as smart buildings, medical implants, and surveillance systems. However, existing devices are bulky, measuring >;1cm3, and they are hampered by short lifetimes and fail to realize the “smart dust” vision of [1]. Smart dust requires a mm3-scale, wireless sensor node with perpetual energy harvesting. Recently two application-specific implantable microsystems [2][3] demonstrated the potential of a mm3-scale system in medical applications. However, [3] is not programmable and [2] lacks a method for re-programming or re-synchronizing once encapsulated. Other practical issues remain unaddressed, such as a means to protect the battery during the time period between system assembly and deployment and the need for flexible design to enable use in multiple application domains.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123011738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 116
Towards ultra-dense arrays of VHF NEMS with FDSOI-CMOS active pixels for sensing applications 面向传感应用的具有FDSOI-CMOS有源像素的VHF NEMS超密集阵列
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6177005
G. Arndt, C. Dupré, J. Arcamone, G. Cibrario, O. Rozeau, L. Duraffourg, E. Ollier, É. Colinet
{"title":"Towards ultra-dense arrays of VHF NEMS with FDSOI-CMOS active pixels for sensing applications","authors":"G. Arndt, C. Dupré, J. Arcamone, G. Cibrario, O. Rozeau, L. Duraffourg, E. Ollier, É. Colinet","doi":"10.1109/ISSCC.2012.6177005","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177005","url":null,"abstract":"This paper presents the first realization of a fully co-integrated single-crystal NEMS resonator and its CMOS electronics on a single chip. The CMOS technol ogy is based on a \"home-made\" 0.3μm fully depleted (FD) SOI technology. The resonator fabricated from the SOI silicon layer in a top-down front-end VLSI process is actuated thanks to electrostatic forces. The vibrations are detected differentially with two p-doped silicon piezoresistive (PZR) gauges. Details concerning the NEMS-FD SOI CMOS technological process can also be found in [3] while this paper primarily reports on the design of the circuitry and its first electrical measurements.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124736706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology 采用32nm SOI CMOS技术的28Gb/s 4分路FFE/15分路DFE串行链路收发器
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6177031
J. Bulzacchelli, T. Beukema, D. Storaska, Ping-Hsuan Hsieh, S. Rylov, Daniel Furrer, Daniele Gardellini, A. Prati, C. Menolfi, D. Hanson, J. Hertle, T. Morf, Vivek Sharma, R. Kelkar, H. Ainspan, W. Kelly, G. Ritter, Jon Garlett, R. Callan, T. Toifl, D. Friedman
{"title":"A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology","authors":"J. Bulzacchelli, T. Beukema, D. Storaska, Ping-Hsuan Hsieh, S. Rylov, Daniel Furrer, Daniele Gardellini, A. Prati, C. Menolfi, D. Hanson, J. Hertle, T. Morf, Vivek Sharma, R. Kelkar, H. Ainspan, W. Kelly, G. Ritter, Jon Garlett, R. Callan, T. Toifl, D. Friedman","doi":"10.1109/ISSCC.2012.6177031","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177031","url":null,"abstract":"As exemplified by standards such as OIF CEI-25G, 32G-FC, and next-generation 100GbE, serial link data rates are being pushed up to 25 to 28Gb/s in order to increase I/O system bandwidth. Such speeds represent a near doubling of the state-of-the-art for fully integrated transceivers [1-3]. With scaling no longer providing large gains in device speed, significant design advances must be made to attain these data rates. This paper describes a 28Gb/s serial link transceiver featuring a source-series terminated (SST) driver topology with twice the speed of existing designs, a two-stage peaking amplifier with capacitively-coupled parallel input stages and active feedback, and a 15-tap DFE. The use of capacitive level-shifters allows a single current-integrating summer to drive the parallel paths used for speculating the first two DFE taps.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124843656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 60
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