2012 IEEE International Solid-State Circuits Conference最新文献

筛选
英文 中文
A DC-to-1GHz tunable RF ΔΣ ADC achieving DR = 74dB and BW = 150MHz at f0 = 450MHz using 550mW 一个dc - 1ghz可调谐RF ΔΣ ADC,在f0 = 450MHz使用550mW时实现DR = 74dB和BW = 150MHz
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6176954
H. Shibata, R. Schreier, Wenhua Yang, A. Shaikh, D. Paterson, T. Caldwell, D. Alldred, P. Lai
{"title":"A DC-to-1GHz tunable RF ΔΣ ADC achieving DR = 74dB and BW = 150MHz at f0 = 450MHz using 550mW","authors":"H. Shibata, R. Schreier, Wenhua Yang, A. Shaikh, D. Paterson, T. Caldwell, D. Alldred, P. Lai","doi":"10.1109/ISSCC.2012.6176954","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176954","url":null,"abstract":"The ultimate ADC for receiver applications would be one that converts any desired RF signal directly into digital form so that the rest of the signal chain enjoys accurate and flexible digital signal processing and CMOS scaling. Flexibility in center frequency (f0), bandwidth (BW), sampling frequency (fS), full-scale (FS), dynamic range (DR) and power consumption (P) would allow the ADC to handle multiple standards and adapt to the RF environment [1-4]. The ADC reported in this paper is a step toward this Holy Grail of ADCs, supporting fο = 0 to 1 GHz, BW = 35 to 150MHz, fS = 2 to 4GHz and FS = -18dBm to +18dBm. At f0 = 450MHz, BW = 150MHz, fS = 4GHz and FS = +6dBm, the ADC achieves instantaneous DR = 74dB and peak SNR = 69dB with P = 550mW.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123167568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS 采用32nm CMOS的280mv -1.2 v宽工作范围IA-32处理器
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6176932
Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, S. Ramani, S. Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, R. Ramanarayanan, V. Erraguntla, J. Howard, S. Vangal, S. Dighe, G. Ruhl, Paolo A. Aseron, H. Wilson, N. Borkar, V. De, S. Borkar
{"title":"A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS","authors":"Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, S. Ramani, S. Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, R. Ramanarayanan, V. Erraguntla, J. Howard, S. Vangal, S. Dighe, G. Ruhl, Paolo A. Aseron, H. Wilson, N. Borkar, V. De, S. Borkar","doi":"10.1109/ISSCC.2012.6176932","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176932","url":null,"abstract":"Near-threshold computing brings the promise of an order of magnitude improvement in energy efficiency over the current generation of microprocessors [1]. However, frequency degradation due to aggressive voltage scaling may not be acceptable across all single-threaded or performance-constrained applications. Enabling the processor to operate over a wide voltage range helps to achieve best possible energy efficiency while satisfying varying performance demands of the applications. This paper describes an IA-32 processor fabricated in 32nm CMOS technology [2], demonstrating a reliable ultra-low voltage operation and energy efficient performance across the wide voltage range from 280mV to 1.2V.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116764827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 212
A batteryless 19μW MICS/ISM-band energy harvesting body area sensor node SoC 无电池19μW MICS/ ism波段能量采集体面积传感器节点SoC
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6177004
Fan Zhang, Yanqing Zhang, J. Silver, Y. Shakhsheer, M. Nagaraju, Alicia Klinefelter, J. Pandey, James Boley, E. Carlson, A. Shrivastava, B. Otis, B. Calhoun
{"title":"A batteryless 19μW MICS/ISM-band energy harvesting body area sensor node SoC","authors":"Fan Zhang, Yanqing Zhang, J. Silver, Y. Shakhsheer, M. Nagaraju, Alicia Klinefelter, J. Pandey, James Boley, E. Carlson, A. Shrivastava, B. Otis, B. Calhoun","doi":"10.1109/ISSCC.2012.6177004","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177004","url":null,"abstract":"Recent advances in ultra-low power chip design techniques, many originally targeting wireless sensor networks, will enable a new generation of body-worn devices for health monitoring. We utilize the state-of-the-art in low power RF transmitters, low voltage boost circuits, subthreshold processing, biosignal front-ends, dynamic power management, and energy harvesting to realize an integrated reconfigurable wireless body-area-sensor node (BASN) SoC capable of autonomous power management for battery-free operation.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121277002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 110
A 7-to-10b 0-to-4MS/s flexible SAR ADC with 6.5-to-16fJ/conversion-step 7- 10b 0- 4ms /s灵活SAR ADC,转换步长6.5- 16fj
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6177096
P. Harpe, Yan Zhang, G. Dolmans, K. Philips, H. D. Groot
{"title":"A 7-to-10b 0-to-4MS/s flexible SAR ADC with 6.5-to-16fJ/conversion-step","authors":"P. Harpe, Yan Zhang, G. Dolmans, K. Philips, H. D. Groot","doi":"10.1109/ISSCC.2012.6177096","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177096","url":null,"abstract":"Applications like wireless sensor nodes require ultra-low-power ADCs. However, each application has different requirements for accuracy and bandwidth. Recent power-efficient ADCs for sensor applications are mostly designed for a fixed accuracy and a limited range of sample rates. An efficiently scalable sample rate (10kS/s to 10MS/s) has been demonstrated before, but without scalability of resolution. In, an ADC with both flexible resolution and sample rate is reported; however, its power efficiency is not as good as the point-solutions in. This paper describes a SAR ADC that achieves both good power efficiency (6.5-to-16fJ/conversion-step) and a wide range of flexibility (7-to-10b resolution, sample rates up to 4MS/s) to cover a large variety of applications, thereby reducing cost, design-time and overall complexity. To optimize the power efficiency for each resolution, both the DAC and comparator are reconfigurable. A 2-step conversion scheme is proposed for 9 and 10b settings to further reduce the power consumption. Finally, the use of an asynchronous architecture and dynamic circuitry ensures that the power consumption scales inherently proportional to the sample rate.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127484461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 96
A 1920×1080 3.65μm-pixel 2D/3D image sensor with split and binning pixel structure in 0.11pm standard CMOS 一个1920×1080 3.65μm像素2D/3D图像传感器,在0.11pm标准CMOS上具有拆分和分组像素结构
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6177063
Seong-Jin Kim, Byongmin Kang, James D. K. Kim, KeeChang Lee, Chang-Yeong Kim, Kinam Kim
{"title":"A 1920×1080 3.65μm-pixel 2D/3D image sensor with split and binning pixel structure in 0.11pm standard CMOS","authors":"Seong-Jin Kim, Byongmin Kang, James D. K. Kim, KeeChang Lee, Chang-Yeong Kim, Kinam Kim","doi":"10.1109/ISSCC.2012.6177063","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177063","url":null,"abstract":"In this paper, we present a 2nd-generation 2D/3D imager based on the pinned- photodiode pixel structure. The time-division readout architecture for both image types (color and depth) is maintained. A complete redesign of the imager makes pixels smaller and more sensitive than before. To obtain reliable depth information using a pinned-photodiode, a depth pixel is split into eight small pieces for high-speed charge transfer, and demodulated electrons are merged into one large storage node, enabling phase delay measurement with 52.8% demodulation contrast at 20MHz frequency. Furthermore, each split pixel gener- ates its own color information, offering a 2D image with full-HD resolution (1920x1080).","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125586291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS 基于32nm CMOS的1.45GHz 52 ~ 162gflops /W可变精度浮点融合乘加单元
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6176987
Himanshu Kaul, M. Anders, S. Mathew, S. Hsu, A. Agarwal, F. Sheikh, R. Krishnamurthy, S. Borkar
{"title":"A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS","authors":"Himanshu Kaul, M. Anders, S. Mathew, S. Hsu, A. Agarwal, F. Sheikh, R. Krishnamurthy, S. Borkar","doi":"10.1109/ISSCC.2012.6176987","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176987","url":null,"abstract":"High-throughput floating-point computations are key building blocks of 3D graphics, signal processing and high-performance computing workloads [1,2]. Higher floating-point precisions offer improved accuracy at the expense of performance and energy efficiency, with variable-precision floating-point circuits providing run-time precision selection [3]. Real-time certainty tracking enables variable-precision circuits not only to operate at the higher energy efficiency of low-precision datapaths, but also to preserve high-precision accuracy. A variable-precision floating-point unit that performs fused multiply-adds (FMA) with single-cycle throughput while supporting operation in either 1-way single-precision (24b mantissa), 2-way 12b precision or 4-way 6b precision modes is fabricated in 32nm High-k/Metal-gate CMOS [4]. Simultaneous floating-point certainty tracking, preshifted addends, a combined rounding and negation incrementer, efficient reuse of mantissa datapath for multiple parallel lower precision calculations, robust ultra-low voltage circuits, and fine-grained clock gating enable nominal energy efficiency of 52GFLOPS/W (IEEE 32b single-precision, measured at 1.45GHz, 1.05V, 25°C) with a dense layout occupying 0.045mm2 (Fig. 10.3.7) while achieving: (i) scalable performance up to 3.6GFLOPS (single-precision), 96mW measured at 1.2V; (ii) up to 4× higher throughput of 14.4GFLOPS with variable-precision, while maintaining single-precision accuracy; (iii) fast single-cycle precision reconfigurability; (iv) precision mode-dependent power consumption for up to 40% clock power reduction; (v) near-threshold single-precision operation measured at 300mV, 1.75MHz, 11μW; and, (vi) peak energy efficiency of 321GFLOPS/W (single-precision) and 1.2TFLOPS/W (6b precision) at 325mV, 25°C.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117255663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
An interference-aware 5.8GHz wake-up radio for ETCS 用于ETCS的干扰感知5.8GHz唤醒无线电
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6177084
Jeongki Choi, Kanghyuk Lee, Seok-Oh Yun, Sang-Gug Lee, J. Ko
{"title":"An interference-aware 5.8GHz wake-up radio for ETCS","authors":"Jeongki Choi, Kanghyuk Lee, Seok-Oh Yun, Sang-Gug Lee, J. Ko","doi":"10.1109/ISSCC.2012.6177084","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177084","url":null,"abstract":"Wake-up radios have been a popular transceiver architecture in recent years for battery-powered applications such as wireless body area networks (WBANs) [1], wireless sensor networks (WSNs) [2,3], and even electronic toll collection systems (ETCS) [4]. The most important consideration in implementing a wake-up receiver (WuRX) is low power dissipation while maximizing sensitivity. Because of this requirement of very low power, WuRX are usually designed by a simple RF envelope detector (RFED) consisting of Schottky diodes [1,3] or MOSFETs in the weak inversion region [2] without active filtering or amplification of the input signal. Therefore, the performance of the RFED itself is critical for attaining good sensitivity of the WuRX. Moreover, the poor filtering of the input signal renders the WuRX vulnerable to interferers from nearby terminals with high transmit power such as mobile phones and WiFi devices, and this can result in false wake-ups [1]. Although the RFED has very low power, a false wake-up will increase the power consumption of the wake-up radio as it will enable the power-hungry main transceiver.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128405620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
A maximum power-point tracker without digital signal processing in 0.35μm CMOS for automotive applications 无数字信号处理的0.35μm CMOS最大功率点跟踪器,用于汽车应用
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6176894
R. Enne, M. Nikolic, H. Zimmermann
{"title":"A maximum power-point tracker without digital signal processing in 0.35μm CMOS for automotive applications","authors":"R. Enne, M. Nikolic, H. Zimmermann","doi":"10.1109/ISSCC.2012.6176894","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176894","url":null,"abstract":"In the upcoming field of e-mobility roof-integrated photovoltaic systems are used to extend the cruising range of electric vehicles. Due to the roof's curvature the solar cells (SC) show different inclination angles to the sunlight, resulting in different maximum power points (MPP) and a lower harvested energy if all SCs are controlled by a centralized MPP-regulated DC/DC converter. A further issue is partial shading. The use of smart modules where a smaller SC number is tied to a module-integrated converter with MPP tracking (MPPT) improves the system efficiency. Current smart module controllers like the SPV1020 [5] use ADCs for voltage and current measurements together with digital processing. Quasi-analog MPPT methods for system-on-chip implementation in this field of application are discussed and tested [1,2] but not realized as ICs. In the field of energy harvesting for micro power applications converters with integrated analogue MPPT are already implemented [3] but the quality of the MPP regulation is too poor for the use in smart modules.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129273334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
A 1.0TOPS/W 36-core neocortical computing processor with 2.3Tb/s Kautz NoC for universal visual recognition 1.0TOPS/W 36核新皮质计算处理器,2.3Tb/s Kautz NoC,用于通用视觉识别
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6177099
Chuan-Yung Tsai, Yu-Ju Lee, Chun-Ting Chen, Liang-Gee Chen
{"title":"A 1.0TOPS/W 36-core neocortical computing processor with 2.3Tb/s Kautz NoC for universal visual recognition","authors":"Chuan-Yung Tsai, Yu-Ju Lee, Chun-Ting Chen, Liang-Gee Chen","doi":"10.1109/ISSCC.2012.6177099","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177099","url":null,"abstract":"In this paper, an NC processor for power-efficient real-time universal visual recognition is proposed with following features: 1) A grey matter-like homogeneous many-core architecture with event-driven hybrid MIMD execution provides 1.0TOPS/W efficient acceleration for NC operations; 2) A white matter-like Kautz NoC provides 2.3Tb/s throughput, fault/congestion avoidance and redundancy-free multicast with 151Tb/s/W NoC power efficiency, which is 2.7-3.9x higher than previous NoC-based visual recognition processors.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127017360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A capacitive touch controller robust to display noise for ultrathin touch screen displays 一种对超薄触摸屏显示噪声具有鲁棒性的电容式触摸控制器
2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI: 10.1109/ISSCC.2012.6176943
Kiduk Kim, S. Byun, Yoon-Kyung Choi, J. Baek, Hwa-Hyun Cho, Jong-kang Suwon Park, Hae-Yong Ahn, Chang-Ju Lee, Min-Soo Cho, Joo-Hyeon Lee, Sang-Woo Kim, Hyung-Dal Kwon, Yong-Yeob Choi, Hosuk Na, Junchul Park, Yeonwoo Shin, Kyungsuk Jang, Gyoo-cheol Hwang, Myunghee Lee
{"title":"A capacitive touch controller robust to display noise for ultrathin touch screen displays","authors":"Kiduk Kim, S. Byun, Yoon-Kyung Choi, J. Baek, Hwa-Hyun Cho, Jong-kang Suwon Park, Hae-Yong Ahn, Chang-Ju Lee, Min-Soo Cho, Joo-Hyeon Lee, Sang-Woo Kim, Hyung-Dal Kwon, Yong-Yeob Choi, Hosuk Na, Junchul Park, Yeonwoo Shin, Kyungsuk Jang, Gyoo-cheol Hwang, Myunghee Lee","doi":"10.1109/ISSCC.2012.6176943","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176943","url":null,"abstract":"Capacitive touch screens have become widely adopted in mobile applications. Capacitive touch-screen display modules have conventionally been assembled by bonding two separate modules: 1) a touch-screen module with touch panel glass or film attached to the cover window, and 2) a display module, with a small air gap between them. An important role of the air gap is to decrease capacitive coupling of display noise to the sensors, and it is very effective since permittivity of air is more than 4χ lower than that of glass.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129070347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信