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1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines最新文献

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Expressing dynamic reconfiguration by partial evaluation 通过部分求值表示动态重构
1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines Pub Date : 1996-04-17 DOI: 10.1109/FPGA.1996.564830
Satnam Singh, Jonathan D. Hogg, D. McAuley
{"title":"Expressing dynamic reconfiguration by partial evaluation","authors":"Satnam Singh, Jonathan D. Hogg, D. McAuley","doi":"10.1109/FPGA.1996.564830","DOIUrl":"https://doi.org/10.1109/FPGA.1996.564830","url":null,"abstract":"Dynamic reconfiguration of FPGAs is a powerful technique for modifying a circuit as it executes. However, dynamic reconfiguration is inadequately supported by CAD tools and poorly understood in general. We present a specific class of dynamic reconfigurations that can be expressed in terms of a formalism called partial evaluation. This provides a systematic framework for understanding the effect of a dynamic reconfiguration, as well as providing guidance on how to complete specialised circuits. The primary advantages of this technique are circuits which are smaller and faster for a certain class of applications. We present one case study from the ATM field which benefits from this treatment.","PeriodicalId":244873,"journal":{"name":"1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines","volume":"23 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123732057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
Using MORRPH in an industrial machine vision system MORRPH在工业机器视觉系统中的应用
1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines Pub Date : 1996-04-17 DOI: 10.1109/FPGA.1996.564738
IV WilliamE.King, T. Drayer, R. Conners, P. Araman
{"title":"Using MORRPH in an industrial machine vision system","authors":"IV WilliamE.King, T. Drayer, R. Conners, P. Araman","doi":"10.1109/FPGA.1996.564738","DOIUrl":"https://doi.org/10.1109/FPGA.1996.564738","url":null,"abstract":"This paper describes the use of the MORRPH board (an FPGA-based CCM) in an industrial machine vision system. The system is designed to solve the color sorting problem in the furniture manufacturing industry. This entails classifying wooden samples (staves) into one of several predetermined color classes, so that all members of a particular class \"match\". In this system, two MORRPH boards are used to perform the \"early\" processing, including: field-of-view operators, light-intensity monitoring, shading correction background extraction, color-quantization, gray-scale channel generation, and histogram generation. This functionality utilizes the following MORRPH board features: open support sockets are filled with various SRAMs depending on necessary requirements, functionality is time-multiplexed by reprogramming the FPGAs, one of three I/O Busses is used for high-bandwidth input of color camera data, the ISA Bus interface is used for low-bandwidth output of histogram data, user-programmable ports allow simple modification of operating parameters. The use of two MORRPH boards to perform the early processing provides almost 200 times the overall system throughput when compared to a system that used two 486-based PCs to perform the \"early\" processing.","PeriodicalId":244873,"journal":{"name":"1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131895428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Supporting FPGA microprocessors through retargetable software tools 通过可重新定位的软件工具支持FPGA微处理器
1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines Pub Date : 1996-04-17 DOI: 10.1109/FPGA.1996.564836
David A. Clark, B. Hutchings
{"title":"Supporting FPGA microprocessors through retargetable software tools","authors":"David A. Clark, B. Hutchings","doi":"10.1109/FPGA.1996.564836","DOIUrl":"https://doi.org/10.1109/FPGA.1996.564836","url":null,"abstract":"FPGA systems outperform many ASIC and supercomputer systems through effective use of the reconfigurable resource. Reusing design effort across different applications requires a standard, flexible software environment. Driving FPGA systems from ANSI C is possible using 1 cc (an ANSI C compiler) targeted at an FPGA system and dasm (a retargetable, flexible assembler). The compiler supports custom hardware capabilities of FPGA systems, as well as all constructs of C. The assembler reads instruction definitions at assemble time, allowing the user to add new custom hardware functions which dasm can assemble correctly to an instruction stream the hardware executes. A source code debugger has been implemented for this system.","PeriodicalId":244873,"journal":{"name":"1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125085717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Using rapid prototyping to teach the design of complete computing solutions 使用快速原型来教授完整计算解决方案的设计
1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines Pub Date : 1996-04-17 DOI: 10.1109/FPGA.1996.564752
P. Athanas, R. D. Hudson
{"title":"Using rapid prototyping to teach the design of complete computing solutions","authors":"P. Athanas, R. D. Hudson","doi":"10.1109/FPGA.1996.564752","DOIUrl":"https://doi.org/10.1109/FPGA.1996.564752","url":null,"abstract":"Sound preparation for a career in computing systems design includes articulation in computer architecture and organization, compiler design, and operating systems. Contemporary instructional approaches towards this collective topic address each of the components in isolation. When taught in isolation, the interaction and trade-offs between the system hardware and the system software, while being critical factors for determining system performance, may not be adequately stressed. This paper presents a course structure which combines computer architecture, computer design, and system software design to convey the principals of constructing contemporary general-purpose computing solutions. Rapid prototyping technology is utilized in the laboratory component of the course for implementing full-custom processors, which are used as platforms for executing and evaluating prototype software.","PeriodicalId":244873,"journal":{"name":"1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122885298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Aizup-a pipelined processor design and implementation on XILINX FPGA chip aizup -一种基于XILINX FPGA芯片的流水线处理器设计与实现
1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines Pub Date : 1996-04-17 DOI: 10.1109/FPGA.1996.564755
Yamin Li, Wanming Chu
{"title":"Aizup-a pipelined processor design and implementation on XILINX FPGA chip","authors":"Yamin Li, Wanming Chu","doi":"10.1109/FPGA.1996.564755","DOIUrl":"https://doi.org/10.1109/FPGA.1996.564755","url":null,"abstract":"This paper describes a pipelined processor (named Aizup) design and implementation for the exercise of Computer Architecture/Organization Education at the University of Aizu. The Aizup, pipeline has four stages and deals with data dependency and control dependency. The Aizup was designed at Cadence environment and implemented on Xilinx XC4006PC84 FPGA chip. We ask students to design the processor, to perform functional simulations, to implement the design on the chip, and to measure the chip with logic analyzer. The exercise course is helpful to students to understand the operations of pipelined processors and to master the design methodologies and the use of measuring instruments.","PeriodicalId":244873,"journal":{"name":"1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115598444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Mixing fixed and reconfigurable logic for array processing 混合固定和可重构逻辑阵列处理
1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines Pub Date : 1996-04-17 DOI: 10.1109/FPGA.1996.564766
P. Bakkes, J. D. Plessis, B. Hutchings
{"title":"Mixing fixed and reconfigurable logic for array processing","authors":"P. Bakkes, J. D. Plessis, B. Hutchings","doi":"10.1109/FPGA.1996.564766","DOIUrl":"https://doi.org/10.1109/FPGA.1996.564766","url":null,"abstract":"This paper describes the architecture of the MIX system that was designed to investigate the trade-off between the use of reconfigurable and fixed logic. The calculation of the dot-product of two vectors of 32 bit floating point numbers, that forms the basis of array processing in many engineering applications, is used as the basic algorithm for the investigation. The results indicate that fixed logic is more suited for floating point units and memories while reconfigurable logic is useful for implementing control logic providing significant flexibility. It was also found that the additional delay in reconfigurable logic can effectively overlap with the operating time of the fixed logic subsystems. The advantage of reconfigurability of the control is therefore combined with the high bandwidth properties of the fixed logic.","PeriodicalId":244873,"journal":{"name":"1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129620371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A software development system for FPGA-based data acquisition systems 基于fpga的数据采集系统的软件开发系统
1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines Pub Date : 1996-04-17 DOI: 10.1109/FPGA.1996.564739
A. Wenban, Geoffrey M. Brown
{"title":"A software development system for FPGA-based data acquisition systems","authors":"A. Wenban, Geoffrey M. Brown","doi":"10.1109/FPGA.1996.564739","DOIUrl":"https://doi.org/10.1109/FPGA.1996.564739","url":null,"abstract":"We present a compiler, debugger, linker, and hardware/software interface for data acquisition systems based on hardware that is reconfigurable by the end user. Unlike earlier work, we choose a source language which is software-oriented. Our goal is to make systems with reconfigurable hardware accessible to scientists and engineers who are competent programmers but are not hardware literate.","PeriodicalId":244873,"journal":{"name":"1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122057848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A PCI-compatible FPGA-coprocessor for 2D/3D image processing 用于2D/3D图像处理的pci兼容fpga协处理器
1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines Pub Date : 1996-04-17 DOI: 10.1109/FPGA.1996.564782
G. Knittel
{"title":"A PCI-compatible FPGA-coprocessor for 2D/3D image processing","authors":"G. Knittel","doi":"10.1109/FPGA.1996.564782","DOIUrl":"https://doi.org/10.1109/FPGA.1996.564782","url":null,"abstract":"We present a small-scale FPGA-coprocessor board for PCI-based systems. It features one XC3195A FPGA (<9 K gate equivalents), three XC4013 devices (each up to 13 K gate equivalents), 2 MByte of Flash Memory, 256 KByte of high-speed SRAM and a 16-bit high-speed multiply-and-accumulate unit. The board was designed to speed up algorithms from scientific visualization, in particular the visualization of 3D-datasets. Such algorithms show a large number of short integer or bit operations, which can efficiently be off-loaded from the CPU to an FPGA-coprocessor. Although being exactly tailored to our application, the accelerator constitutes a versatile platform for other algorithms from image or speech processing. The PCI-bus provides the necessary transfer bandwidth for dataflow-intensive computations.","PeriodicalId":244873,"journal":{"name":"1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122480485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Assessing document relevance with run-time reconfigurable machines 评估文档与运行时可重构机器的相关性
1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines Pub Date : 1996-04-17 DOI: 10.1109/FPGA.1996.564737
B. Gunther, G. Milne, V. Narasimhan
{"title":"Assessing document relevance with run-time reconfigurable machines","authors":"B. Gunther, G. Milne, V. Narasimhan","doi":"10.1109/FPGA.1996.564737","DOIUrl":"https://doi.org/10.1109/FPGA.1996.564737","url":null,"abstract":"Free text database searching is a natural candidate for acceleration by run time reconfigurable custom computing machines. We describe a fully pipelined search machine architecture for scoring the relevance of textual documents against approximately 100 relevant target words, with provision for limited regular expression matching and error tolerance. An implementation on the SPACE custom computing platform indicates that throughput in the order of 20 megabytes per second is achievable on ALgotronix FPGAs if a locally synchronous design style is adopted and global communications minimized. Partial reconfiguration of the datapath at run time, in around 3 seconds, serves to maximize the density of data storage on the machine and correspondingly avoid costly input from the environment.","PeriodicalId":244873,"journal":{"name":"1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126914197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
RACER: a reconfigurable constraint-length 14 Viterbi decoder RACER:一个可重构的约束长度14维特比解码器
1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines Pub Date : 1996-04-17 DOI: 10.1109/FPGA.1996.564746
D. Yeh, G. Feygin, P. Chow
{"title":"RACER: a reconfigurable constraint-length 14 Viterbi decoder","authors":"D. Yeh, G. Feygin, P. Chow","doi":"10.1109/FPGA.1996.564746","DOIUrl":"https://doi.org/10.1109/FPGA.1996.564746","url":null,"abstract":"This paper describes the architecture and implementation of a constraint-length 14 Viterbi decoder that achieves a decoding rate of 41 Kbits/s. The system uses 36 Xilinx XC4010 FPGAs with seven processor cards and a custom backplane to implement a multi-ring general cascade Viterbi decoder architecture. The paper also shows how to achieve decoding rates of 1 Mbit/s using current FPGA technology. Comparisons are made to JPL's big Viterbi decoder, which uses custom ASICs.","PeriodicalId":244873,"journal":{"name":"1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125641121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
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