{"title":"The PIG paradigm: the design and use of a massively parallel fine grained self-reconfigurable infinitely scalable architecture","authors":"N. Macias","doi":"10.1109/EH.1999.785450","DOIUrl":"https://doi.org/10.1109/EH.1999.785450","url":null,"abstract":"The requirements of a general purpose massively parallel processing system are outlined. The suitability of a fine-grained self-reconfigurable system to general massively parallel processing is shown. A new type of self-reconfigurable device called the PIG is introduced, and details of its design and operation are explained. The PIG's uniqueness compared to other reconfigurable systems is discussed. This uniqueness is further illustrated through specific examples of PIG circuits. An application of the PIG to evolvable hardware is described. Further potential applications are discussed. Plans for future work, including options for building a large-scale PIG are discussed.","PeriodicalId":234639,"journal":{"name":"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130222171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A system for intrinsic evolution of linear and non-linear filters","authors":"S. J. Flockton, K. Sheehan","doi":"10.1109/EH.1999.785440","DOIUrl":"https://doi.org/10.1109/EH.1999.785440","url":null,"abstract":"A system for exploring intrinsic evolution of linear and non-linear filter systems is described. It consists of a testbed topology of operational amplifiers and linear or non-linear passive components together with a control and measurement system for selecting different values and layouts of components and testing the resulting circuit. The results of each measurement can be used by an evolutionary algorithm to search for a good match to a target response.","PeriodicalId":234639,"journal":{"name":"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116036569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Asari, Y. Mitsuyama, T. Onoye, I. Shirakawa, H. Hirano, T. Honda, T. Otsuki, T. Baba, T. Meng
{"title":"FeRAM circuit technology for system on a chip","authors":"K. Asari, Y. Mitsuyama, T. Onoye, I. Shirakawa, H. Hirano, T. Honda, T. Otsuki, T. Baba, T. Meng","doi":"10.1109/EH.1999.785453","DOIUrl":"https://doi.org/10.1109/EH.1999.785453","url":null,"abstract":"The ferroelectric memory (FeRAM) has a great advantage for system on a chip, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM. To enhance the applicability of FeRAM for embedded reconfigurable hardware, three circuit technologies are discussed in this paper. Simulation and measurement data confirmed that both power consumption and memory area can be substantially reduced, making FeRAM the most promising new technology for implementing high-performance, low-power reconfigurable hardware.","PeriodicalId":234639,"journal":{"name":"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware","volume":"399 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121802911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. D. Garis, N. Nawa, A. Buller, M. Korkin, Felix Alexander Gers, M. Hough
{"title":"ATR's artificial brain (\"CAM-Brain\") project: A sample of what individual \"CoDi-1 Bit\" model evolved neural net modules can do with digital and analog I/O","authors":"H. D. Garis, N. Nawa, A. Buller, M. Korkin, Felix Alexander Gers, M. Hough","doi":"10.1109/EH.1999.785441","DOIUrl":"https://doi.org/10.1109/EH.1999.785441","url":null,"abstract":"This work presents a sample of what evolved neural net circuit modules using the socalled \"CoDi-1 Bit\" neural net model can do. This work is part of an 8 year research project at ATR which aims to build an artificial brain containing a billion neurons by the year 2001, that will be used to control the behaviors of a kitten robot \"Robokoneko\". It looks as though the figure is more likely to be 40 million, but the numbers are not of great concern. What is more important is the issue of evolvability of the cellular automata (CA) based neural net circuits which grow and evolve in special FPGA (Field Programmable Gate Array) hardware, at hardware speeds (e.g. updating 150 billion CA cells per second, and performing a complete run of a genetic algorithm, i.e. tens of thousands of circuit growths and fitness evaluations to evolve the elite neural net circuit in about 1 second). The specialized hardware which performs this evolution is labeled the CAM-Brain Machine (CBM). It implements the CoDi-1 Bit model, and was delivered to ATR in May 1999. The CBM should make practical the assemblage of 10,000s of evolved neural net modules into humanly defined artificial brain architectures. For the past few months, the latest hardware version of the CBM has been simulated in software to see just how evolvable and functional individual evolved modules can be. This work reports on some of the results of these simulations, for which the input/output is either binary or analog.","PeriodicalId":234639,"journal":{"name":"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121368727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The evolution of ROBDDs: preliminary results and a first analysis","authors":"P. van Remortel, Tom Lenaerts, B. Manderick","doi":"10.1109/EH.1999.785461","DOIUrl":"https://doi.org/10.1109/EH.1999.785461","url":null,"abstract":"In this paper, we describe and analyze a number of evolutionary experiments concerning reduced ordered binary decision diagrams. These are important representations of Boolean functions for both circuit design and verification, and evolvable hardware. We experiment with the use of cube transformations in the genetic learning of unknown Boolean functions using ROBDDs.","PeriodicalId":234639,"journal":{"name":"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124071139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}