Proceedings of the First NASA/DoD Workshop on Evolvable Hardware最新文献_第3页

GeneticFPGA: evolving stable circuits on mainstream FPGA devices GeneticFPGA:在主流FPGA器件上进化稳定电路

Proceedings of the First NASA/DoD Workshop on Evolvable Hardware Pub Date : 1999-07-19 DOI: 10.1109/EH.1999.785430

Delon Levi, S. Guccione

{"title":"GeneticFPGA: evolving stable circuits on mainstream FPGA devices","authors":"Delon Levi, S. Guccione","doi":"10.1109/EH.1999.785430","DOIUrl":"https://doi.org/10.1109/EH.1999.785430","url":null,"abstract":"GeneticFPGA is a Java-based tool for evolving digital circuits on Xilinx XC4000EX/sup TM/ and XC4000XL/sup TM/ devices. Unlike other FPGA architectures popular with evolutionary hardware researchers, the XC4000 series architectures cannot accept arbitrary configuration data. Only a small subset of configuration bit patterns will produce operational circuits; other configuration bit patterns produce circuits which are unreliable and may even permanently damage the FPGA device. GeneticFPGA uses novel software techniques to produce legal circuit configurations for these devices, permitting experimentation with evolvable hardware on the larger, faster more mainstream devices. In addition, these techniques have led to methods for evolving circuits which are neither temperature, voltage, nor silicon dependent. An 8-bit counter and several digital frequency dividers have been successfully evolved using this approach. GeneticFPGA uses Xilinx's JBits/sup TM/ interface to control the generation of bitstream configuration data and the XHWIF portable hardware interface to communicate with a variety of commercially available FPGA-based hardware. GeneticFPGA, JBits, and XHWIF are currently being ported to the Xilinx Virtex/sup TM/ family of devices, which will provide greatly increased reconfiguration speed and circuit density.","PeriodicalId":234639,"journal":{"name":"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115837930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 49

Coevolutionary robotics 共同进化的机器人

Proceedings of the First NASA/DoD Workshop on Evolvable Hardware Pub Date : 1999-07-19 DOI: 10.1109/EH.1999.785455

J. Pollack, Hod Lipson, Pablo Funes, S. Ficici, G. Hornby

引用次数: 34

Co-evolving demes of non-uniform cellular automata for synchronisation 同步非均匀元胞自动机的协同进化模式

Proceedings of the First NASA/DoD Workshop on Evolvable Hardware Pub Date : 1999-07-19 DOI: 10.1109/EH.1999.785442

Vesselin K. Vassilev, J. Miller, T. Fogarty

引用次数: 3

An applications approach to evolvable hardware 可进化硬件的应用方法

Proceedings of the First NASA/DoD Workshop on Evolvable Hardware Pub Date : 1999-07-19 DOI: 10.1109/EH.1999.785449

R. Porter, K. McCabe, N. Bergmann

引用次数: 22

Evolving wire antennas using genetic algorithms: a review 利用遗传算法进化有线天线:综述

Proceedings of the First NASA/DoD Workshop on Evolvable Hardware Pub Date : 1999-07-19 DOI: 10.1109/EH.1999.785457

D. Linden, E. Altshuler

引用次数: 30

Reconfigurable FPGA's in the 1-20 GHz band with HBT BiCMOS 可重构FPGA在1-20 GHz频段与HBT BiCMOS

Proceedings of the First NASA/DoD Workshop on Evolvable Hardware Pub Date : 1999-07-19 DOI: 10.1109/EH.1999.785452

J. McDonald, B. Goda

{"title":"Reconfigurable FPGA's in the 1-20 GHz band with HBT BiCMOS","authors":"J. McDonald, B. Goda","doi":"10.1109/EH.1999.785452","DOIUrl":"https://doi.org/10.1109/EH.1999.785452","url":null,"abstract":"This paper describes the operation of a field Programmable gate array (FPGA), the basics of current mode logic, and examines the idea of creating a SiGe heterojunction bipolar (HBT) version of the Xilinx 6200 FPGA. A new proposed device would be bitwise compatible with the 6200, but would operate in the 1-20 GHz range due to the HBT technology being used for the logic and routing and CMOS for storing the configuration bits. This is possible due to the IBM cointegration process of a HBT with a BiCMOS process. Information in this paper is based on an HBT having a f/sub T/ of 50 GHz, but later in 1999 IBM will be unveiling a process that will double the speed. By replacing and redesigning key parts of the 6200 FPGA, a 100-200X operating speedup is possible. The core logic cell in the 6200 consists of two input multiplexers and nip-flops, which can easily be converted to current mode logic (CML). Routing in a conventional FPGA is done via pass transistors, which can act like a low pass filter for a high-speed signal. A SiGe HBT CML multiplexer can be used for routing which can pass signals with a 12-14 picoseconds delay. Through the use of a side decoder, memory planes of configuration could be used to store current and future configurations. Interchange could occur between memory planes if the old flip-flop values are stored, new flip-flop values are restored, and then the new configuration plane is activated. Countless applications such as DSP, Ethernet routing, missile control, and artificial intelligence could utilize a SiGe HBT FPGA.","PeriodicalId":234639,"journal":{"name":"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126377325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Reliability analysis in self-repairing embryonic systems 自我修复胚胎系统的可靠性分析

Proceedings of the First NASA/DoD Workshop on Evolvable Hardware Pub Date : 1999-07-19 DOI: 10.1109/EH.1999.785443

C. Ortega-Sanchez, A. Tyrrell

引用次数: 54

Dynamic phase-only array beam control using a genetic algorithm 基于遗传算法的动态纯相阵列波束控制

Proceedings of the First NASA/DoD Workshop on Evolvable Hardware Pub Date : 1999-07-19 DOI: 10.1109/EH.1999.785456

R. Haupt, J. M. Johnson

引用次数: 9

A genetic programming approach to logic function synthesis by means of multiplexers 用多路复用器合成逻辑函数的遗传规划方法

Proceedings of the First NASA/DoD Workshop on Evolvable Hardware Pub Date : 1999-07-19 DOI: 10.1109/EH.1999.785434

A. H. Aguirre, B. Buckles, C. C. Coello

引用次数: 37

Inherent qualities of circuits designed by artificial evolution: a preliminary study of populational fault tolerance 人工进化设计电路的固有特性:群体容错的初步研究

Proceedings of the First NASA/DoD Workshop on Evolvable Hardware Pub Date : 1999-07-19 DOI: 10.1109/EH.1999.785438

P. Layzell

引用次数: 18