{"title":"On the nature of two-bit multiplier landscapes","authors":"Vesselin K. Vassilev, J. Miller, T. Fogarty","doi":"10.1109/EH.1999.785433","DOIUrl":"https://doi.org/10.1109/EH.1999.785433","url":null,"abstract":"The two-bit multiplier is a simple electronic circuit, small enough to be evolvable, and practically useful for the implementation of many digital systems. In this paper we study the structure of the two-bit multiplier fitness landscapes generated by circuit evolution on an idealised model of a field-programmable gate array. The two-bit multiplier landscapes are challenging. The difficulty in studying these landscapes stems from the genotype representation which allows us to evolve the functionality and connectivity of an array of logic cells. Here, the genotypes are simply strings defined over two completely different alphabets. This makes the study of the corresponding landscapes much more involved. We outline a model for studying the two-bit multiplier landscapes and estimate the amplitudes derived from the Fourier transform of these landscape. We show that the two-bit multiplier landscapes can be characterised in terms of subspaces, determined by the interactions between the genotype partitions.","PeriodicalId":234639,"journal":{"name":"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124150223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Lohn, G. Haith, S. Colombano, D. Stassinopoulos
{"title":"A comparison of dynamic fitness schedules for evolutionary design of amplifiers","authors":"J. Lohn, G. Haith, S. Colombano, D. Stassinopoulos","doi":"10.1109/EH.1999.785439","DOIUrl":"https://doi.org/10.1109/EH.1999.785439","url":null,"abstract":"High-level analog circuit design is a complex problem domain in which evolutionary search has recently produced encouraging results. However, little is known about how to best structure evolution far these tasks. The choices of circuit representation, fitness evaluation technique, and genetic operators clearly have a profound effect on the search process. In this paper, we examine fitness evaluation by comparing the effectiveness of four fitness schedules. Three fitness schedules are dynamic-the evaluation function changes over the course of the run, and one is static. Coevolutionary search is included, and we present a method of evaluating the problem population that is conducive to multiobjective optimization. Twenty-five runs of an analog amplifier design task using each fitness schedule are presented. The results indicate that solution quality is highest with static and coevolving fitness schedules as compared to the other two dynamic schedules. We discuss these results and offer two possible explanations for the observed behavior: retention of useful information, and alignment of problem difficulty with circuit proficiency.","PeriodicalId":234639,"journal":{"name":"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115205117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Representation and robustness for evolved sorting networks","authors":"J. Masner, J. Cavalieri, J. Frenzel, J. Foster","doi":"10.1109/EH.1999.785462","DOIUrl":"https://doi.org/10.1109/EH.1999.785462","url":null,"abstract":"We describe evolved sorting networks for a Xilinx 6200 rapidly reconfigurable Field Programmable Gate Array (FPGA) and for a simulated environment. Our goal was to evaluate the efficiency and stability of evolved circuits in a changing environment. Not only did we evolve correct sorting networks, but we also examined the representations of evolved individuals for their runtime efficiency and effectiveness. We compared three different hardware representations: tree structured encodings, linear direct encodings, and raw configuration files. We also used three separate fitness functions. We also present an interesting metric for gate-level resilience to faults: bitwise stability. We find evidence that evolution inherently improves bitwise stability, and that tree structures may confer more bitwise stability than linear structured chromosomes.","PeriodicalId":234639,"journal":{"name":"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132510978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Moreno, J. Madrenas, J. Cabestany, E. Cantó, R. Kiełbik, J. Faura, J. Insenser
{"title":"Realization of self-repairing and evolvable hardware structures by means of implicit self-configuration","authors":"J. Moreno, J. Madrenas, J. Cabestany, E. Cantó, R. Kiełbik, J. Faura, J. Insenser","doi":"10.1109/EH.1999.785451","DOIUrl":"https://doi.org/10.1109/EH.1999.785451","url":null,"abstract":"In this paper we shall address the physical implementation of self-repairing and evolvable hardware strategies. These alternatives will be enabled by the specific dynamic reconfiguration capabilities included in a new family of FPGA devices, called FIPSOC (Field programmable System On a Chip). The main features of these devices are given by the integration on a single chip of a dynamically reconfigurable FPGA, a programmable analog section and a microcontroller. As our experimental results will show, the efficient use of the available resources makes these devices an excellent platform for testing, developing and realizing physically new concepts in electronic design.","PeriodicalId":234639,"journal":{"name":"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132007279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Evolving more efficient digital circuits by allowing circuit layout evolution and multi-objective fitness","authors":"T. Kalganova, J. Miller","doi":"10.1109/EH.1999.785435","DOIUrl":"https://doi.org/10.1109/EH.1999.785435","url":null,"abstract":"We use evolutionary search to design combinational logic circuits. The technique is based on evolving the functionality and connectivity of a rectangular array of logic cells whose dimension is defined by the circuit layout. The main idea of this approach is to improve quality of the circuits evolved by the genetic algorithm (GA) by reducing the number of active gates used. We accomplish this by combining two ideas: 1) using multi-objective fitness function; 2) evolving circuit layout. It will be shown that using these two approaches allows us to increase the quality of evolved circuits. The circuits are evolved in two phases. Initially the genome fitness is given by the percentage of output bits that are correct. Once 100% functional circuits have been evolved, the number of gates actually used in the circuit is taken into account in the fitness function. This allows us to evolve circuits with 100% functionality and minimise the number of active gates in circuit structure. The population is initialised with heterogeneous circuit layouts and the circuit layout is allowed to vary during the evolutionary process. Evolving the circuit layout together with the function is one of the distinctive features of proposed approach. The experimental results show that allowing the circuit layout to be flexible is useful when we want to evolve circuits with the smallest number of gates used. We find that it is better to use a fixed circuit layout when the objective is to achieve the highest number of 100% functional circuits. The two-fitness strategy is most effective when we allow a large number of generations.","PeriodicalId":234639,"journal":{"name":"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115041709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A model for dynamic adaptation in reconfigurable hardware systems","authors":"G. Milne","doi":"10.1109/EH.1999.785448","DOIUrl":"https://doi.org/10.1109/EH.1999.785448","url":null,"abstract":"A theory is presented in which to model the changing structure found in reconfigurable computing devices and which provides a foundation for developing the languages necessary to program such devices. The core concept is that of a complex system of agents which interact with each other over a changing, connective topological structure. The agents themselves may be created, destroyed and evolve in a biological-like manner These concepts and the manner in which they are harnessed within the dsCircal model are presented in this paper. The relationship between these concepts and reconfigurable evolvable hardware is outlined, giving a basis for a compilation mechanism allowing the high-level programming of dynamically changing hardware systems.","PeriodicalId":234639,"journal":{"name":"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130119056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Morphogenesis in plants: modeling the shoot apical meristem, and possible applications","authors":"E. Mjolsness, E. Meyerowitz, V. Gor, T. Mann","doi":"10.1109/EH.1999.785445","DOIUrl":"https://doi.org/10.1109/EH.1999.785445","url":null,"abstract":"A key determinant of overall morphogenesis in flowering plants such as Arabidopsis thaliana is the shoot apical meristem (growing tip of a shoot). Gene regulation networks can be used to model this system. We exhibit a very preliminary two-dimensional model including gene regulation and intercellular signaling, but omitting cell division and dynamical geometry. The model can be trained to have three stable regions of gene expression corresponding to the central zone, peripheral zone, and rib meristem. We also discuss a space-engineering motivation for studying and controlling the morphogenesis of plants using such computational models.","PeriodicalId":234639,"journal":{"name":"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128372819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimization for aerospace conceptual design through the use of genetic algorithms","authors":"W. Crossley","doi":"10.1109/EH.1999.785454","DOIUrl":"https://doi.org/10.1109/EH.1999.785454","url":null,"abstract":"Using a genetic algorithm (GA) as a non-calculus-based global search method allows optimization-like techniques to be applied in the conceptual phase of design, which traditionally has been dominated by qualitative or subjective decision making. Features of the GA provide several advantages for conceptual design including: the ability to combine discrete, integer and continuous variables, the population-based search, no requirement for an initial design, and the ability to address non-convex, multimodal and discontinuous functions. Examples of applications to aerospace system conceptual design include aerospace vehicle design and satellite constellation design. A multiobjective design approach using the GA is also discussed.","PeriodicalId":234639,"journal":{"name":"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127378447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Guangming Lu, H. Singh, Ming-Hau Lee, N. Bagherzadeh, F. Kurdahi, E. Filho, V. Alves
{"title":"The MorphoSys dynamically reconfigurable system-on-chip","authors":"Guangming Lu, H. Singh, Ming-Hau Lee, N. Bagherzadeh, F. Kurdahi, E. Filho, V. Alves","doi":"10.1109/EH.1999.785447","DOIUrl":"https://doi.org/10.1109/EH.1999.785447","url":null,"abstract":"MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity dynamic reconfigurability and considerable depth of programmability. The first implementation of the MorphoSys architecture, the M1 chip, is currently at an advanced stage and it will operate at 100 MHz. Simulation results indicate significant performance improvements for different classes of applications, as compared to general-purpose processors. Meanwhile, MorphoSys can provide the potential hardware platforn for the evolvable hardware (EH) simulation with the help of the software.","PeriodicalId":234639,"journal":{"name":"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131360605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improving correctness of finite-state machine synthesis from multiple partial input/output sequences","authors":"P. Chongstitvatana, C. Aporntewan","doi":"10.1109/EH.1999.785463","DOIUrl":"https://doi.org/10.1109/EH.1999.785463","url":null,"abstract":"Our previous work focused on the synthesis of sequential circuits based on a partial input/output sequence. As the behavioural description of the target circuit is not known the correctness of the result can not be verified. This paper proposes a method which increases the correctness percentage of the finite-state machine (FSM) synthesis using multiple partial input/output sequences. The synthesizer is based on genetic algorithm. The experimental results show that the correctness percentage can be increased to 100% by increasing the number of input/output sequences.","PeriodicalId":234639,"journal":{"name":"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125036785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}