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2010 12th Biennial Baltic Electronics Conference最新文献

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Reconfigurable data acquisition unit for bioimpedance measurements 用于生物阻抗测量的可重构数据采集单元
2010 12th Biennial Baltic Electronics Conference Pub Date : 2010-11-11 DOI: 10.1109/BEC.2010.5630891
V. Pesonen, M. Gorev, P. Annus, Mart Min, P. Ellervee
{"title":"Reconfigurable data acquisition unit for bioimpedance measurements","authors":"V. Pesonen, M. Gorev, P. Annus, Mart Min, P. Ellervee","doi":"10.1109/BEC.2010.5630891","DOIUrl":"https://doi.org/10.1109/BEC.2010.5630891","url":null,"abstract":"Multi-channel data-acquisition devices are used often in biomedicine to measure properties of organs/tissues. A DSP-based solution for a multi-frequency measurement unit has been proposed and implemented. In this paper, extensions to the existing prototype data acquisition unit are discussed. The extensions were designed to allow to reduce the aliasing effect.","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130258256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High accuracy, low temperature coefficient bandgap voltage reference 精度高，带隙基准电压温度系数低
2010 12th Biennial Baltic Electronics Conference Pub Date : 2010-11-11 DOI: 10.1109/BEC.2010.5630057
S. Strik, V. Strik
{"title":"High accuracy, low temperature coefficient bandgap voltage reference","authors":"S. Strik, V. Strik","doi":"10.1109/BEC.2010.5630057","DOIUrl":"https://doi.org/10.1109/BEC.2010.5630057","url":null,"abstract":"The design of CMOS bandgap voltage references focusing on high accuracy and low temperature coefficient methodologies is discussed in this paper. Several solutions of total bandgap voltage reference error minimization are considered. As a summary it is proposed bandgap voltage reference with output voltage accuracy 1.2V ± 0.08% in temperature range −40∶125°C.","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"320 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134043492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Exploitation of scattered context grammars to model VLIW instruction constraints 利用分散上下文语法对VLIW指令约束进行建模
2010 12th Biennial Baltic Electronics Conference Pub Date : 2010-11-11 DOI: 10.1109/BEC.2010.5630284
J. Kroustek, S. Židek, D. Kolář, A. Meduna
{"title":"Exploitation of scattered context grammars to model VLIW instruction constraints","authors":"J. Kroustek, S. Židek, D. Kolář, A. Meduna","doi":"10.1109/BEC.2010.5630284","DOIUrl":"https://doi.org/10.1109/BEC.2010.5630284","url":null,"abstract":"More and more nowadays data processing System-on-Chip (SoC) devices exploit the very long instruction word (VLIW) technology. The high performance of VLIW processors is achieved by a high instruction level parallelism. Program execution is scheduled statically at compilation time. Therefore, there is no need for run-time control mechanisms and hardware can be relatively simple. On the other hand, all constraints checks must be done by the compiler. This paper describes formal method for modeling instruction level limitations of these processors. This method is based on scattered context grammars that generate proper assembler code. This concept has two advantages - formal description of the dependency checking process and high reduction of description complexity over other methods.","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129859204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A power-on reset with accurate hysteresis 具有精确滞后的上电复位
2010 12th Biennial Baltic Electronics Conference Pub Date : 2010-11-11 DOI: 10.1109/BEC.2010.5631522
A. Kalanti, L. Aaltonen, M. Paavola, M. Kamarainen, M. Pulkkinen, K. Halonen
{"title":"A power-on reset with accurate hysteresis","authors":"A. Kalanti, L. Aaltonen, M. Paavola, M. Kamarainen, M. Pulkkinen, K. Halonen","doi":"10.1109/BEC.2010.5631522","DOIUrl":"https://doi.org/10.1109/BEC.2010.5631522","url":null,"abstract":"As the complexity of the digital circuit blocks continues to increase, a power-on reset, POR, circuit is needed to initialize the digital logic to the known state at the start-up. This paper represents a POR with thresholds that are insensitive to the rise time of the supply voltage. This is achieved by generating the POR pulse with a constant current reference circuit. Moreover, current mirroring is used to improve hysteresis. The designed POR has a quiescent current of 3.1 µA (VDD=3.6 V) and operates with supplies ranging from 3 V to 3.6 V. The area of the circuit is 109.9 µm × 106.65 µm and the chip was implemented with triple-well 0.35 µm HVCMOS process.","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130369372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Register-transfer level deductive fault simulation using decision diagrams 使用决策图的寄存器传输级演绎故障仿真
2010 12th Biennial Baltic Electronics Conference Pub Date : 2010-11-11 DOI: 10.1109/BEC.2010.5631842
U. Reinsalu, J. Raik, R. Ubar
{"title":"Register-transfer level deductive fault simulation using decision diagrams","authors":"U. Reinsalu, J. Raik, R. Ubar","doi":"10.1109/BEC.2010.5631842","DOIUrl":"https://doi.org/10.1109/BEC.2010.5631842","url":null,"abstract":"The paper presents a deductive method for register-transfer level fault simulation on the system model of high-level decision diagrams. The method is based on the bit coverage fault model, which has been proven to have a good correspondence with gate-level structural faults. Experiments on ITC99 benchmark circuits have been carried out showing the feasibility of the proposed approach.","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"354 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132582051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
On-line monitoring of dialysis adequacy using DiaSens optical sensor: Accurate Kt/V estimation by smoothing algorithms 使用DiaSens光学传感器在线监测透析充分性:通过平滑算法精确估计Kt/V
2010 12th Biennial Baltic Electronics Conference Pub Date : 2010-11-11 DOI: 10.1109/BEC.2010.5630164
A. Talisainen, S. Kostin, D. Karai, I. Fridolin, R. Ubar
{"title":"On-line monitoring of dialysis adequacy using DiaSens optical sensor: Accurate Kt/V estimation by smoothing algorithms","authors":"A. Talisainen, S. Kostin, D. Karai, I. Fridolin, R. Ubar","doi":"10.1109/BEC.2010.5630164","DOIUrl":"https://doi.org/10.1109/BEC.2010.5630164","url":null,"abstract":"Objective: develop signal processing algorithm for the removal of disturbances not related to treatment course and compare with available clinical data.","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123710601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High power, zero ripples active filtering system with power modules operating in parallel 大功率、零波纹有源滤波系统，功率模块并联工作
2010 12th Biennial Baltic Electronics Conference Pub Date : 2010-11-11 DOI: 10.1109/BEC.2010.5630014
D. Wojciechowski, R. Strzelecki
{"title":"High power, zero ripples active filtering system with power modules operating in parallel","authors":"D. Wojciechowski, R. Strzelecki","doi":"10.1109/BEC.2010.5630014","DOIUrl":"https://doi.org/10.1109/BEC.2010.5630014","url":null,"abstract":"The paper present the model based predictive controller for ripple free, high power active filter (APF) with LCL circuit. The system suppresses LCL resonance and provides control dynamics limited only by circuit parameters. The inverter of an active power filter requires a high PWM switching frequency, therefore high power application has to be realized by using several power modules operating in parallel. There are presented simulations and experimental results achieved for APF system of the rated power 1.2MVA with four 300 kVA power blocks operating in parallel.","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122383205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low power CMOS current source for shortened square wave signals 用于缩短方波信号的低功率CMOS电流源
2010 12th Biennial Baltic Electronics Conference Pub Date : 2010-11-11 DOI: 10.1109/BEC.2010.5629899
A. Kasemaa, T. Rang
{"title":"Low power CMOS current source for shortened square wave signals","authors":"A. Kasemaa, T. Rang","doi":"10.1109/BEC.2010.5629899","DOIUrl":"https://doi.org/10.1109/BEC.2010.5629899","url":null,"abstract":"The paper gives short overview of an efficient CMOS technology based current source realization and layout design. The current source output will be shortened square wave signal [1],[2] and [3]. The output current value can be selected from range 5 to 100µA. The current source layout design needs good matching, the geometry and temperature influence has been analyzed and the optimal geometrical structure will be suggested.","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116839161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Timed Automata based provably correct robot control 基于时间自动机的可证明正确的机器人控制
2010 12th Biennial Baltic Electronics Conference Pub Date : 2010-11-11 DOI: 10.1109/BEC.2010.5631008
A. Anier, J. Vain
{"title":"Timed Automata based provably correct robot control","authors":"A. Anier, J. Vain","doi":"10.1109/BEC.2010.5631008","DOIUrl":"https://doi.org/10.1109/BEC.2010.5631008","url":null,"abstract":"This paper presents a feasibility study on the usage of Uppaal Timed Automata (UPTA) for deliberative level robotic control. The study is based on the Scrub Nurse Robot case-study. Our experience confirms that UPTA model based control enables the control loop to be defined and maintained during the robot operation autonomously with minimum human intervention. Specifically, in our robot architecture the control model is constructed automatically using unsupervised learning. Correctness of the model is verified on-the-fly against safety, reachability, and performance requirements. Finally, it is demonstrated that UPTA model based robot control, action planning and model updates have natural implementation based on existing model execution and conformance testing tool Uppaal Tron.","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129963344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
EMC of converters for interlocking device 联锁装置用变换器的电磁兼容性
2010 12th Biennial Baltic Electronics Conference Pub Date : 2010-11-11 DOI: 10.1109/BEC.2010.5630881
R. Dolecek, Jaroslav Novak, O. Černý, Zdenek Nemec
{"title":"EMC of converters for interlocking device","authors":"R. Dolecek, Jaroslav Novak, O. Černý, Zdenek Nemec","doi":"10.1109/BEC.2010.5630881","DOIUrl":"https://doi.org/10.1109/BEC.2010.5630881","url":null,"abstract":"The paper deals with the problems of Electromagnetic Compatibility (EMC) of the frequency control drive of the electromotive switch actuator of the railway switch. The frequency converter with Pulse Width Modulation (PWM) and the output sinus filter are used for feeding of the asynchronous motor of the switch actuator. This drive is operated in the isolated system of feeding voltages. The drive is fed by the frequency converter with unshielded cable with length up to 1.2 km. The EMC problems occurring at development and operating of drive are analyzed in this paper. This paper completes and specifies [1].","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130201120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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