2017 International Conference on Networking, Architecture, and Storage (NAS)最新文献

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Data Block Partitioning for Recovering Stuck-at Faults in PCMs 基于数据块分区的pcm卡滞故障恢复
2017 International Conference on Networking, Architecture, and Storage (NAS) Pub Date : 2017-08-01 DOI: 10.1109/NAS.2017.8026850
Marjan Asadinia, Majid Jalili, H. Sarbazi-Azad
{"title":"Data Block Partitioning for Recovering Stuck-at Faults in PCMs","authors":"Marjan Asadinia, Majid Jalili, H. Sarbazi-Azad","doi":"10.1109/NAS.2017.8026850","DOIUrl":"https://doi.org/10.1109/NAS.2017.8026850","url":null,"abstract":"Main burdens to the DRAM scalability are leakage and charge storage restrictions. Phase Change Memory (PCM) is being known as a promising candidate for the replacement of DRAM among competitive non-volatile memories. However, this memory suffers from low cell reliability due to limited write endurance. This problem can lead to some memory cells permanently stuck at either '0' or '1'. Therefore, a robust error recovery scheme is needed to overcome this problem and recover from hard errors. State-of-the-art solutions apply error correction and recovery techniques at inter- line or intra-line level. Precisely, they can improve PCM endurance either by remapping failed lines to spares (in inter-line level schemes) or by using data-block partitioning and bit- inversion scheme (in intra-line level schemes). Although techniques of the latter type are effective, proper partitioning of data blocks and spreading out faults across different groups are required. In this paper, we propose and evaluate a novel intra-line level scheme that statically partition a data-block into some groups and efficiently recover multi-bit stuck-at faults per partition. This method benefits from the advantage of a simple shifting mechanism in order to increase the chance of storing data in presence of failed cells. Evaluation results for multi- threaded workloads show enhancement in the number of recoverable failures and improvement of lifetime over existing techniques.","PeriodicalId":222161,"journal":{"name":"2017 International Conference on Networking, Architecture, and Storage (NAS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124075484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Automatic Collector for Dynamic Cloud Performance Information 动态云性能信息自动采集器
2017 International Conference on Networking, Architecture, and Storage (NAS) Pub Date : 2017-08-01 DOI: 10.1109/NAS.2017.8026845
Olaf Elzinga, Spiros Koulouzis, Arie Taal, Junchao Wang, Yang Hu, Huan Zhou, Paul Martin, C. D. Laat, Zhiming Zhao
{"title":"Automatic Collector for Dynamic Cloud Performance Information","authors":"Olaf Elzinga, Spiros Koulouzis, Arie Taal, Junchao Wang, Yang Hu, Huan Zhou, Paul Martin, C. D. Laat, Zhiming Zhao","doi":"10.1109/NAS.2017.8026845","DOIUrl":"https://doi.org/10.1109/NAS.2017.8026845","url":null,"abstract":"When deploying an application in the cloud, a developer often wants to know which of the wide variety of cloud resources is best to use. Most cloud providers only provide static information about different cloud resources which is often not enough because static information does not take into account the hardware and software that is being used or the policy that has been applied by the cloud provider. Therefore, dynamic benchmarking of cloud resources is needed to find out how a certain workload is going to behave on a certain instance. However, benchmarking various cloud resources is a time consuming process. Thus, using a tool which automatically benchmarks various cloud resources will be of great use. % To maximize the effectiveness of such a tool, it will be helpful to maintain an up to date cloud information catalogue, so that users can share and compare their benchmark results to the results of other users. In this paper, we present the Cloud Performance Collector, a modular cloud benchmarking tool aimed to automatically benchmark a wide variety of applications. To demonstrate the benefit of the tool, we did three experiments with three synthetic benchmark applications and one real-world application using the ExoGENI testbed.","PeriodicalId":222161,"journal":{"name":"2017 International Conference on Networking, Architecture, and Storage (NAS)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115927159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
SimpleBP: A Lightweight Branch Prediction Simulator for Effective Design Exploration SimpleBP:用于有效设计探索的轻量级分支预测模拟器
2017 International Conference on Networking, Architecture, and Storage (NAS) Pub Date : 2017-08-01 DOI: 10.1109/NAS.2017.8026877
Chaobing Zhou, Libo Huang, Zhisheng Li, Q. Dou
{"title":"SimpleBP: A Lightweight Branch Prediction Simulator for Effective Design Exploration","authors":"Chaobing Zhou, Libo Huang, Zhisheng Li, Q. Dou","doi":"10.1109/NAS.2017.8026877","DOIUrl":"https://doi.org/10.1109/NAS.2017.8026877","url":null,"abstract":"Besides the accuracy of prediction, chip area occupancy and power consumption also should be taken into account in the design of branch predictors. Many of the previous prediction simulation platforms have either only considered accuracy computed with coarse-grained updating model, or just been the low-speed full system simulators. In this paper, We presents SimpleBP, a lightweight prediction simulator based on trace driven. It leverages the SystemC language to simulate branch predictor at clock cycle granularity. And the CACTI model is introduced to evaluate area and power consumption. The experiment results show that SimpleBP can accurately give multiple evaluations of branch predictors.","PeriodicalId":222161,"journal":{"name":"2017 International Conference on Networking, Architecture, and Storage (NAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115316050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
FlashStorageSim: Performance Modeling for SSD Architectures FlashStorageSim: SSD架构的性能建模
2017 International Conference on Networking, Architecture, and Storage (NAS) Pub Date : 2017-08-01 DOI: 10.1109/NAS.2017.8026860
Krishna T. Malladi, Mu-Tien Chang, Dimin Niu, Hongzhong Zheng
{"title":"FlashStorageSim: Performance Modeling for SSD Architectures","authors":"Krishna T. Malladi, Mu-Tien Chang, Dimin Niu, Hongzhong Zheng","doi":"10.1109/NAS.2017.8026860","DOIUrl":"https://doi.org/10.1109/NAS.2017.8026860","url":null,"abstract":"We present FlashStorageSim, an SSD architecture performance model for data center servers, validated with an enterprise SSD. In addition to the SSD controller, SSD organization, and flash devices, FlashStorageSim models the host interface (e.g., SATA, PCIe, DDR). This allows users to explore non-traditional SSD use cases. We also implement mechanisms to improve simulation speed, which is shown to reduce simulation time by more than 7X. We show how FlashStorageSim can help researchers understand SSD design decisions.","PeriodicalId":222161,"journal":{"name":"2017 International Conference on Networking, Architecture, and Storage (NAS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124813522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
hpFog: A FPGA-Based Fog Computing Platform hpFog:基于fpga的雾计算平台
2017 International Conference on Networking, Architecture, and Storage (NAS) Pub Date : 2017-08-01 DOI: 10.1109/NAS.2017.8026862
Tze Hon Tan, C. Y. Ooi, M. N. Marsono
{"title":"hpFog: A FPGA-Based Fog Computing Platform","authors":"Tze Hon Tan, C. Y. Ooi, M. N. Marsono","doi":"10.1109/NAS.2017.8026862","DOIUrl":"https://doi.org/10.1109/NAS.2017.8026862","url":null,"abstract":"This paper presents a versatile high performance FPGA-based Fog platform to accommodate the growth of Internet-of-Thing. Proposed platform allows hosted Fog applications to have high throughput computation while retaining required flexibility for post-deployment functional updates. Significantly, proposed platform has remote connectivity to allow customized circuitry of hosted applications to be software-defined by external management or development entity once deployed. Proposed platform occupied less than 14% of slices and 15% of BRAM logic resources in FPGA, which left more than 86% of slices and 85% of BRAM for application plane implementation.","PeriodicalId":222161,"journal":{"name":"2017 International Conference on Networking, Architecture, and Storage (NAS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131883199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
DD-L1D: Improving the Decoupled L1D Efficiency for GPU Architecture DD-L1D:提高GPU架构的解耦L1D效率
2017 International Conference on Networking, Architecture, and Storage (NAS) Pub Date : 2017-08-01 DOI: 10.1109/NAS.2017.8026851
Weiguang Yang, Yuxin Wang, Yulong Yu, Guang-yuan Kan, He Guo
{"title":"DD-L1D: Improving the Decoupled L1D Efficiency for GPU Architecture","authors":"Weiguang Yang, Yuxin Wang, Yulong Yu, Guang-yuan Kan, He Guo","doi":"10.1109/NAS.2017.8026851","DOIUrl":"https://doi.org/10.1109/NAS.2017.8026851","url":null,"abstract":"GPU L1 data cache contention, caused by a huge amount of concurrent threads, leads to insufficient cache utilization and poor performance, especially for cache unfriendly applications. Cache bypassing is a widely- used method to alleviate this problem, and Decoupled L1D (D-L1D) is a preventive bypassing scheme, which achieves performance improvement for cache unfriendly applications by considering the data locality of memory access streams. However, our experiments and analyses show that limited performance gain by D-L1D is attained due to the pre-defined locality threshold. To address this issue, we propose a novel bypassing scheme named as Dynamic D-L1D (DD-L1D) that directs the L1 data cache to the less contention by dynamically updating the locality threshold during runtime. We evaluate four metrics in DD-L1D to indicate the L1 cache bypassing state, and choose bypassing miss rate in our final configuration. The experimental results demonstrate that DD-L1D improves the baseline performance by 1.45X on average for cache unfriendly benchmarks. It also outperforms D-L1D and the state-of-the-art GPU cache bypassing schemes with lower hardware overhead and memory traffic.","PeriodicalId":222161,"journal":{"name":"2017 International Conference on Networking, Architecture, and Storage (NAS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123358243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
ALARM: A Location-Aware Redistribution Method to Improve 3D FG NAND Flash Reliability 报警:一种提高3D FG NAND闪存可靠性的位置感知重新分配方法
2017 International Conference on Networking, Architecture, and Storage (NAS) Pub Date : 2017-08-01 DOI: 10.1109/NAS.2017.8026841
Yue Zhu, Fei Wu, Qin Xiong, Zhonghai Lu, C. Xie
{"title":"ALARM: A Location-Aware Redistribution Method to Improve 3D FG NAND Flash Reliability","authors":"Yue Zhu, Fei Wu, Qin Xiong, Zhonghai Lu, C. Xie","doi":"10.1109/NAS.2017.8026841","DOIUrl":"https://doi.org/10.1109/NAS.2017.8026841","url":null,"abstract":"3D NAND flash memory is enjoying an increasing popularity as it dramatically increases the bit density, presenting a grand opportunity to satisfy the growing demand on the storage capacity. However, this vertically stacked structure also introduces more serious read disturb problems compared with planar flash devices. Characterization results show that the read disturb errors on 3D floating gate (FG) MLC NAND flash chips exhibit a large discrepancy on the locations and types of pages, implying that pages should not be treated equally when designing migration schemes. This paper makes a thorough observation on read access characteristics by analyzing contemporary workloads collected from a wide range of applications with various read ratios. Based on the characterization results, we build a read disturb error model and propose a location-aware redistribution method (ALARM) that utilizes the intrinsic characteristics of the 3D floating gate NAND flash and redistributes read-hot pages to locations inducing less read disturb errors to improve its reliability. We implement the read disturb error model and our proposed design on an event-driven simulator, and the experimental results show that ALARM can reduce the maximum and average raw bit error rates (RBERs) by up to 99.49% and 91.80% with an operation overhead of 0.70%.","PeriodicalId":222161,"journal":{"name":"2017 International Conference on Networking, Architecture, and Storage (NAS)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134511048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Revisiting Updating Schemes for Erasure-Coded In-Memory Stores 重新审视擦除编码内存存储的更新方案
2017 International Conference on Networking, Architecture, and Storage (NAS) Pub Date : 2017-08-01 DOI: 10.1109/NAS.2017.8026875
Jie Xia, Jianzhong Huang, X. Qin, Q. Cao, C. Xie
{"title":"Revisiting Updating Schemes for Erasure-Coded In-Memory Stores","authors":"Jie Xia, Jianzhong Huang, X. Qin, Q. Cao, C. Xie","doi":"10.1109/NAS.2017.8026875","DOIUrl":"https://doi.org/10.1109/NAS.2017.8026875","url":null,"abstract":"Erasure coding has been gradually adopted by existing data-intensive in-memory stores for 'hot' data; small writes lead to expensive updating overheads in such in-memory stores characterized by update-heavy workloads. There is a pressing demand to address the issue of data updates for erasure-coded in-memory stores. We revisit existing updating schemes in erasure-coded storage clusters by investigating the applicability of these updating schemes to erasure-coded in- memory stores. After an intensive analysis, we propose a grouping-update mechanism - GU - to handle small writes in in-memory stores. With GU in place, requests in an updating window are categorized into several updating groups, where multiple small updates in the same stripe can be executed concurrently. Furthermore, we bring forward a hybrid-updating scheme - Hybrid-U - to minimize total updating I/Os over network under common writes (e.g., small and large writes). We evaluate four dedicated updating schemes, four GU- based updating schemes and Hybrid-U. Our experiments illustrate that GU-based updating schemes and Hybrid-U outperform the four dedicated updating schemes in terms of updating time.","PeriodicalId":222161,"journal":{"name":"2017 International Conference on Networking, Architecture, and Storage (NAS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115490695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Privacy-Protected Data Collection in Wireless Medical Sensor Networks 无线医疗传感器网络中隐私保护的数据收集
2017 International Conference on Networking, Architecture, and Storage (NAS) Pub Date : 2017-08-01 DOI: 10.1109/NAS.2017.8026872
Md. Zakirul Alam Bhuiyan, Mdaliuz Zaman, Guojun Wang, Tian Wang, Jie Wu
{"title":"Privacy-Protected Data Collection in Wireless Medical Sensor Networks","authors":"Md. Zakirul Alam Bhuiyan, Mdaliuz Zaman, Guojun Wang, Tian Wang, Jie Wu","doi":"10.1109/NAS.2017.8026872","DOIUrl":"https://doi.org/10.1109/NAS.2017.8026872","url":null,"abstract":"Medical data collection in healthcare monitoring applications through traditional frameworks raise serious concerns of patient data privacy and security, due to numerous security threats and attacks. In this paper, we investigate the concerns with privacy protected data collection and propose a novel patient privacy protected data collection framework with the aim to provide patient data privacy. We present a new secrete sharing scheme and a share reconstruction scheme for patient data privacy. We consider a distributed database consisting of multiple edge servers and each server receives a share of the patient data. Implementation result shows that secret share generation and sharing reconstruction do not require much computation time.","PeriodicalId":222161,"journal":{"name":"2017 International Conference on Networking, Architecture, and Storage (NAS)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115879929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Contact Duration-Aware Routing in Delay Tolerant Networks 容忍延迟网络中的接触感知时间路由
2017 International Conference on Networking, Architecture, and Storage (NAS) Pub Date : 2017-08-01 DOI: 10.1109/NAS.2017.8026849
Tuan Le, M. Gerla
{"title":"Contact Duration-Aware Routing in Delay Tolerant Networks","authors":"Tuan Le, M. Gerla","doi":"10.1109/NAS.2017.8026849","DOIUrl":"https://doi.org/10.1109/NAS.2017.8026849","url":null,"abstract":"Delay Tolerant Networks (DTNs) are sparse mobile ad-hoc networks in which there is typically no complete path between the source and destination. While much work has been done in the design of forwarding algorithms, little work has focused on studying forwarding under the presence of short contact durations. In this paper, we study a single- copy contact duration-aware (CDA) routing strategy. We address two key issues: (1) to which next hop relay node should messages be forwarded and (2) in which order should messages be forwarded. To reduce the transmission cost, we select relay nodes from both current and past contacts based on the one-hop and two-hop delivery probability, respectively. We derive the delivery probability from the distribution of contact duration time and inter- contact time. For the message scheduling, messages with the highest delivery probability are prioritized to be transmitted first. Extensive simulation results based on the Cabspotting trace show that our scheme can achieve up to 13% higher delivery rate, 12% lower delay, and 23% lower transmission cost compared to other routing strategies.","PeriodicalId":222161,"journal":{"name":"2017 International Conference on Networking, Architecture, and Storage (NAS)","volume":"5 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132524896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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