IEEE SoutheastCon 2008最新文献_第8页

Evolving an emotion-based neural control architecture 进化一种基于情绪的神经控制体系结构

IEEE SoutheastCon 2008 Pub Date : 2008-04-03 DOI: 10.1109/SECON.2008.4494328

N. Ackovska, S. Bozinovski, L. Bozinovska

引用次数: 1

Evaluating mobile phone handoff behavior using chi-square statistical test 用卡方统计检验评价手机交接行为

IEEE SoutheastCon 2008 Pub Date : 2008-04-03 DOI: 10.1109/SECON.2008.4494322

S.A. Rajput, A. Pandya, S. Saxena, S. Ostroff

{"title":"Evaluating mobile phone handoff behavior using chi-square statistical test","authors":"S.A. Rajput, A. Pandya, S. Saxena, S. Ostroff","doi":"10.1109/SECON.2008.4494322","DOIUrl":"https://doi.org/10.1109/SECON.2008.4494322","url":null,"abstract":"Mobile networks reuse frequency bands based on a color map to increase the capacity of the network. A handoff should occur when a mobile unit moves from the influence of one base station with weaker signal into another's that has stronger signal. Handoff behavior of all units is an important factor in quality of service of a mobile phone service. Handoff decisions, also called mobility decisions, are made by mobile phone based on the observed power from base stations. Premature, delayed or exceedingly sensitive decisions are considered poor decisions. Excessive poor decisions result in degradation of service quality in otherwise a healthy mobile system. Conventional research focuses on improving hand-off algorithms. Most of the published work on verification of effectiveness of handoff algorithms is analytical or focuses on data collected under pristine laboratory conditions. A unit that makes good mobility decisions, theoretically or in the laboratory, may not behave as expected in the real world however. We propose a process of evaluating hand off behavior using large amount of diagnostic phone data collected in the real world that is used for identification of adverse trends or aberrant behavior of various models. In this paper, we discuss a chi-square statistical test to evaluate the performance of specific mobile unit model by comparing the behavior of a test mobile unit against a well- established behavior profile. If the behavior of the test model deviates significantly from the well-established profile, it is considered deficient in its handoff behavior that deserves further analysis. The test was developed in such a way that a large amount of units can quickly be tested. The same test can be used to compare performance of all mobile phones in one region to performance of same mobile phones in other regions. Furthermore, our test is useful in determining difference of handoff behavior when the mobile units are moving in opposite directions.","PeriodicalId":188817,"journal":{"name":"IEEE SoutheastCon 2008","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124287086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Introducing SB-CoRLA, a schema-based constructivist robot learning architecture 介绍基于模式的建构主义机器人学习架构SB-CoRLA

IEEE SoutheastCon 2008 Pub Date : 2008-04-03 DOI: 10.1109/SECON.2008.4494288

Yifan Tang, L. Parker

引用次数: 0

Easy-to-use communication interfaces for data acquisition 易于使用的通信接口的数据采集

IEEE SoutheastCon 2008 Pub Date : 2008-04-03 DOI: 10.1109/SECON.2008.4494269

G. Singh, J. Conrad

引用次数: 3

Computing the VCO sweep rate limit for a second-order PLL 计算二阶锁相环的压控振荡器扫描速率限制

IEEE SoutheastCon 2008 Pub Date : 2008-04-03 DOI: 10.1109/SECON.2008.4494256

John L. Stensby

{"title":"Computing the VCO sweep rate limit for a second-order PLL","authors":"John L. Stensby","doi":"10.1109/SECON.2008.4494256","DOIUrl":"https://doi.org/10.1109/SECON.2008.4494256","url":null,"abstract":"Phase-locked loops serve important roles in receivers, coherent transponders and similar radio-frequency-based applications. For many of these uses, the bandwidth of the loop must be kept small to limit the detrimental influence of noise, and this requirement makes the natural PLL pull-in process too slow and/or unreliable. To aid the acquisition process in these cases, an external sweep voltage can be applied to the VCO when the loop is unlocked. Hopefully, the sweep voltage will effect a rapid decrease in closed-loop frequency error to a point where phase lock is achieved quickly. For a second-order loop containing a perfect integrator loop filter, there is a maximum VCO sweep rate magnitude, denoted as Rm rad/sec2, for which phase lock is guaranteed. If the actual VCO sweep rate magnitude is less than Rm, the loop cannot sweep past a stable phase-lock state without locking correctly. For an applied sweep rate greater than Rm, the loop may sweep past a lock point and fail to achieve phase lock. In the PLL literature, only a trial-and-error approach has been described for approximating Rm given values of loop damping factor p and natural frequency omegan. Furthermore, no plot exists of Rm/omegan 2 versus rho. This dearth of results is remedied here. A new numerical algorithm is given that converges to the maximum sweep rate magnitude Rm. It is used to generate a plot of Rm/omegan 2 versus rho, a never-before-explored relationship in the PLL literature.","PeriodicalId":188817,"journal":{"name":"IEEE SoutheastCon 2008","volume":"418 1-2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123429669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Development of a virtual level of detail scene graph for terrain modeling in Java3D (non-reviewed) 在Java3D中开发用于地形建模的虚拟细节级场景图(未回顾)

IEEE SoutheastCon 2008 Pub Date : 2008-04-03 DOI: 10.1109/SECON.2008.4494297

M. Pendergast

{"title":"Development of a virtual level of detail scene graph for terrain modeling in Java3D (non-reviewed)","authors":"M. Pendergast","doi":"10.1109/SECON.2008.4494297","DOIUrl":"https://doi.org/10.1109/SECON.2008.4494297","url":null,"abstract":"Summary form only given. Three-dimensional modeling of geographic information systems has become a reality due to the low cost of relatively powerful workstations, improved performance and memory capabilities of graphics hardware, and the introduction of cross-platform standards such as OpenGL and Java3d. The work presented in this paper is part of an ongoing project whose goal is to create efficient algorithms that support real-time display and fly through capabilities of large virtual world based on NASA and USGS mapping data. The size and resolution of the virtual world should not be limited to the size of RAM or even virtual memory; rather the segments should be loaded, as they are required. This requires the creation of a virtual level of detail segments (LOD) (based on Java3D geometry objects) that are dynamically retrieved as the user moves through the virtual world. To accomplish this it is necessary to have both an efficient storage and retrieval mechanisms and employ efficient rendering techniques. The algorithms employed should use a reasonable amount of disk space and does not unduly burden the network or processor. In addition to having efficient use of resources, the algorithm should minimize visual artefacts associated with LOD processing, namely gaps and checker boarding.","PeriodicalId":188817,"journal":{"name":"IEEE SoutheastCon 2008","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115640560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Probabilistic analysis of the ASW protocol using PRISM 基于PRISM的反潜战协议的概率分析

IEEE SoutheastCon 2008 Pub Date : 2008-04-03 DOI: 10.1109/SECON.2008.4494277

S. Islam, M. Zaid

引用次数: 1

A Study of substrate permittivity effects on the gain of planar inverted-F antennas 基板介电常数对平面倒f天线增益影响的研究

IEEE SoutheastCon 2008 Pub Date : 2008-04-03 DOI: 10.1109/SECON.2008.4494307

Y.-T. Jean-Charles, V. Ungvichian, J. A. Barbosa

引用次数: 3

CMOS-based VLSI design of a specific integrated circuit (ASIC) sensor interface IC chip (non-reviewed) 基于cmos的VLSI专用集成电路(ASIC)传感器接口IC芯片的设计(未回顾)

IEEE SoutheastCon 2008 Pub Date : 2008-04-03 DOI: 10.1109/SECON.2008.4494261

K. Williams, H. Penn, T. Tarver, A. Odeh, Z. Xiao

{"title":"CMOS-based VLSI design of a specific integrated circuit (ASIC) sensor interface IC chip (non-reviewed)","authors":"K. Williams, H. Penn, T. Tarver, A. Odeh, Z. Xiao","doi":"10.1109/SECON.2008.4494261","DOIUrl":"https://doi.org/10.1109/SECON.2008.4494261","url":null,"abstract":"A CMOS-based application specific integrated circuit (ASIC) has been designed, simulated and fabricated for the application of carbon nanotube-based strain sensor interface circuit. The ASIC consists of high performance operational amplifier (OPA), low-pass filter, and 12-bit dual-slope analog-to-digital converter (ADC). The ADC contains an integrator, a comparator, a counter, latch, and digital control logic. The low-pass filter was designed to remove the noise from the sensor. The ASIC was expected to be integrated with a carbon nanotube- based strain sensor to form a strain detection system. The Tanner design tools were used for the design and simulation of the mixed-signal integrated circuit, where L-Edit was used for the layout of circuit and T-SPICE was used for the simulation. Because of the limitation of the 2.2 mm times 2.2 mm chip size for fabrication in MOSIS, we modified the 12-bit ADC into a 4-bit ADC in the ASIC for the fabrication. After layout and post-simulation, the ASIC has been implemented on a 2.2 mm times 2.2 mm silicon chip die and fabricated by using MOSIS AMI 1.5 mum mixed- signal CMOS process technology available through MOSIS.","PeriodicalId":188817,"journal":{"name":"IEEE SoutheastCon 2008","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131591103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis of noise sensitivity and reconstruction accuracy of Tchebichef moments 切比切夫矩噪声敏感性及重构精度分析

IEEE SoutheastCon 2008 Pub Date : 2008-04-03 DOI: 10.1109/SECON.2008.4494350

S. M. Elshoura, D. Megherbi

引用次数: 7