1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)最新文献_第5页

A hierarchical decomposition methodology for multistage clock circuits 多级时钟电路的分层分解方法

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643530

G. Ellis, L. Pileggi, Rob A. Rutenbar

{"title":"A hierarchical decomposition methodology for multistage clock circuits","authors":"G. Ellis, L. Pileggi, Rob A. Rutenbar","doi":"10.1109/ICCAD.1997.643530","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643530","url":null,"abstract":"This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchical decomposition of the layout divides the problem into a set of local Steiner-wired latch clusters (to minimize and balance local capacitance) fed globally by a balanced binary tree (to maximize performance). Second, we recast the global clock distribution problem as a simultaneous optimization of clock topology, clock segment routing, wire sizing and buffering. The hierarchical decomposition reduces the problem complexity and allows use of more aggressive optimization techniques. Integration of the geometric and electrical optimizations likewise allows more aggressive performance goals. Experiments with an industrial design comprising over 16,000 latches demonstrate the efficiency of the approach: a complete clock distribution solution met a 200-MHz cycle time specification with only 310 ps of skew, met strict current density constraints, exhibited good delay matching across uniform wire width and device variations, and was completed in under 10 CPU hours.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114780781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Java as a specification language for hardware-software systems Java作为硬件-软件系统的规范语言

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643613

Rachid Helaihel, K. Olukotun

引用次数: 92

Circuit noise evaluation by Pade approximation based model-reduction techniques 基于Pade近似的模型约简技术的电路噪声评估

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1007/978-1-4615-0292-0_35

P. Feldmann, R. Freund

引用次数: 39

Test and diagnosis of faulty logic blocks in FPGAs fpga中故障逻辑块的测试与诊断

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643618

Sying-Jyan Wang, Tsi-Ming Tsai

引用次数: 48

Fault simulation of interconnect opens in digital CMOS circuits 数字CMOS电路互连开路故障仿真

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643593

H. Konuk

引用次数: 32

A fast and robust exact algorithm for face embedding 一种快速、鲁棒的精确人脸嵌入算法

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/iccad.1997.643534

E. Goldberg, T. Villa, R. Brayton, A. Sangiovanni-Vincentelli

{"title":"A fast and robust exact algorithm for face embedding","authors":"E. Goldberg, T. Villa, R. Brayton, A. Sangiovanni-Vincentelli","doi":"10.1109/iccad.1997.643534","DOIUrl":"https://doi.org/10.1109/iccad.1997.643534","url":null,"abstract":"We present a new matrix formulation of the face hypercube embedding problem that motivates the design of an efficient search strategy to find an encoding that satisfies all faces of minimum length. Increasing dimensions of the Boolean space are explored; for a given dimension constraints are satisfied one at a time. The following features help to reduce the nodes of the solution space that must be explored: candidate cubes instead of candidate codes are generated, cubes yielding symmetric solutions are not generated, a smaller sufficient set of solutions (producing basic sections) is explored, necessary conditions help discard unsuitable candidate cubes, early detection that a partial solution cannot be extended to be a global solution prunes infeasible portions of the search tree. We have implemented a prototype package MINSK based on the previous ideas and run experiments to evaluate it. The experiments show that MINSK is faster and solves more problems than any available algorithm. Moreover, MINSK is a robust algorithm, while most of the proposed alternatives are not. Besides most problems of the complete MCNC benchmark suite, other solved examples include an important set of decoder PLAs coming from the design of microprocessor instruction sets.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130310396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps 行为信号路径建模方法定性洞察和有效的CMOS放大器尺寸

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643563

F. Leyn, W. Daems, G. Gielen, W. Sansen

{"title":"A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps","authors":"F. Leyn, W. Daems, G. Gielen, W. Sansen","doi":"10.1109/ICCAD.1997.643563","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643563","url":null,"abstract":"This paper describes a new modeling methodology that allows to derive systematically behavioral signal path models of operational amplifiers. Combined with symbolic simulation, these models provide high qualitative insight into the small-signal functioning of a circuit. The behavioral signal path model provides compact interpretable expressions for the poles and zeros that constitute the signal path. These expressions show which design parameters have dominant influence on the position of a pole/zero and thus enable a designer to control a manual interactive sizing process. The methodology consists of the application of a sequence of abstractions, so that one gradually progresses from a full device to a full behavior circuit representation. During this translation, qualitative insight and design requirements are obtained. The methodology is implemented in an open tool called EF2ef. The behavioral signal path model is also used for optimization based sizing in order to achieve pole placement in an efficient way. For optimization based siting, a new strategy for hierarchical penalty function composition is proposed, which allows sequential pruning of the design space. Combined with an operating point driven DC formulation and local minimax optimization, a fast sizing method is obtained which can be used for interactive design space exploration. Experimental results of both modeling and siting are shown.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127272624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 33

An exact solution to simultaneous technology mapping and linear placement problem 精确地解决了同步技术映射和线性布局问题

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643610

J. Lou, Amir H. Salek, Massoud Pedram

引用次数: 45

*PHDD: an efficient graph representation for floating point circuit verification *PHDD:浮点电路验证的有效图形表示

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643251

Yirng-An Chen, R. Bryant

引用次数: 46

Adaptive methods for netlist partitioning 网表分区的自适应方法

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643547

Wray L. Buntine, L. Su, A. Newton, Andrew Mayer

{"title":"Adaptive methods for netlist partitioning","authors":"Wray L. Buntine, L. Su, A. Newton, Andrew Mayer","doi":"10.1109/ICCAD.1997.643547","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643547","url":null,"abstract":"An algorithm that remains in use at the core of many partitioning systems is the Kemighan-Lin algorithm and a variant the Fidducia-Matheysses (FM) algorithm. To understand the FM algorithm we applied principles of data engineering where visualization and statistical analysis are used to analyze the run-time behavior. We identified two improvements to the algorithm which, without clustering or an improved heuristic function, bring the performance of the algorithm near that of more sophisticated algorithms. One improvement is based on the observation, explored empirically, that the full passes in the FM algorithm appear comparable to a stochastic local restart in the search. We motivate this observation with a discussion of recent improvements in Monte Carlo Markov Chain methods in statistics. The other improvement is based on the observation that when an FM-like algorithm is run 20 times and the best run chosen, the performance trace of the algorithm on earlier runs is useful data for learning when to abort a later run. These improvements, implemented with a simple adaptive scheme, are orthogonal to techniques used in state-of-the-art implementations, and therefore should be applicable to other VLSI optimization algorithms.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115307914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8