1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)最新文献_第3页

Test generation for primitive path delay faults in combinational circuits 组合电路中原始路径延迟故障的测试生成

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643605

R. Tekumalla, P. R. Menon

引用次数: 20

Trace driven logic synthesis-application to power minimization 跟踪驱动逻辑合成-应用于功率最小化

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643598

L. Carloni, P. McGeer, A. Saldanha, A. Sangiovanni-Vincentelli

引用次数: 0

Low power logic synthesis for XOR based circuits 基于异或电路的低功耗逻辑合成

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643596

U. Narayanan, C. Liu

引用次数: 31

Sequential optimisation without state space exploration 无状态空间探索的序贯优化

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643522

A. Mehrotra, S. Qadeer, V. Singhal, R. Brayton, A. Aziz, A. Sangiovanni-Vincentelli

引用次数: 15

Optimization techniques for high-performance digital circuits 高性能数字电路的优化技术

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1145/266388.266471

C. Visweswariah

{"title":"Optimization techniques for high-performance digital circuits","authors":"C. Visweswariah","doi":"10.1145/266388.266471","DOIUrl":"https://doi.org/10.1145/266388.266471","url":null,"abstract":"The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically transistor and interconnect sizes. The design metrics are not just delay, transition times, power and area, but also signal integrity and manufacturability. This tutorial paper discusses some of the recently proposed methods of circuit optimization, with an emphasis on practical application and methodology impact. Circuit optimization techniques fall into three broad categories. The first is dynamic tuning, based on time-domain simulation of the underlying circuit, typically combined with adjoint sensitivity computation. These methods are accurate but require the specification of input signals, and are best applied to small data-flow circuits and \"cross-sections\" of larger circuits. Efficient sensitivity computation renders feasible the tuning of circuits with a few thousand transistors. Second, static tuners employ static timing analysis to evaluate the performance of the circuit. All paths through the logic are simultaneously turned, and no input vectors are required. Large control macros are best tuned by these methods. However, in the context of deep submicron custom design, the inaccuracy of the delay models employed by these methods often limits their utility. Aggressive dynamic or static tuning can push a circuit into a precipitous corner of the manufacturing process space, which is a problem addressed by the third class of circuit optimization tools, statistical tuners. Statistical techniques are used to enhance manufacturability or maximize yield. In addition to surveying the above techniques, topics such as the use of state-of-the-art nonlinear optimization methods and special considerations for interconnect sizing, clock tree optimization and noise-aware tuning are briefly considered.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133490919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

Partitioning around roadblocks: tackling constraints with intermediate relaxations 围绕障碍进行划分:用中间放松来处理约束

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643546

S. Dutt, Halim Theny

{"title":"Partitioning around roadblocks: tackling constraints with intermediate relaxations","authors":"S. Dutt, Halim Theny","doi":"10.1109/ICCAD.1997.643546","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643546","url":null,"abstract":"Constraint satisfaction during partitioning and placement of VLSI circuits is an important problem, and effective techniques to address it lead to high-quality physical design solutions. This problem has, however been cursorily treated in previous partitioning and placement research. Our work presented here addresses the balance-ratio constraint, and is a crucial first step to an effective solution to the general constraint-satisfaction problem. In current iterative-improvement mincut partitioners, the balance-ratio constraint is tackled by disallowing moves that violate it. These methods can lead to sub-optimal solutions since the process is biased against the movement of large cells and clusters of cells. We present techniques for an informed relaxation process that attempts to estimate whether relaxing the constraint temporarily will ultimately benefit the mincut objective. If so, then a violating move is allowed, otherwise it is disallowed. The violations are corrected in future moves so that the final solution satisfies the given constraint On a set of ACU/SIGDA PROUD benchmark circuits with actual cell sizes, we obtained up to 38% and an average of 14.5% better cutsizes with as little as 13% time overhead using our techniques compared to the standard method of not allowing any relaxation.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116267192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 32

COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits COSMOS: CMOS电路最大功率估计的连续优化方法

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643362

Chuan-Yu Wang, K. Roy

{"title":"COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits","authors":"Chuan-Yu Wang, K. Roy","doi":"10.1109/ICCAD.1997.643362","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643362","url":null,"abstract":"Maximum instantaneous power in VLSI circuits has a great impact on circuit reliability and the design of power and ground lines. To synthesize highly reliable systems, accurate estimates of maximum power must be obtained in various design phases. Unfortunately, determining the input patterns to induce the maximum current (power) is essentially a combinatorial optimization problem. Even for circuits with small number of primary inputs (PI's), it is CPU time intensive to conduct exhaustive search in the input vector space. The only feasible way is to find good upper and lower bounds of the maximum power, and to make the gap between these two bounds as narrow as possible. We present a continuous optimization approach to efficiently generate tight lower bounds of the maximum instantaneous power for CMOS circuits. In our approach, each primary input (PI) of the circuit is allowed to assume any real number between 0 and 1. Maximum power estimation for CMOS circuits is then transformed into a continuous optimization problem, in which a smooth function is maximized over a unit hypercube in the Euclidean space. The continuous problem can be solved efficiently to generate good lower bounds of the maximum power. Our experiments with ISCAS and MCNC benchmark circuits demonstrate the superiority of this approach.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129768680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

BIST TPG for faults in system backplanes 用于系统背板故障的TPG

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643568

Chen-Huan Chiang, S. Gupta

{"title":"BIST TPG for faults in system backplanes","authors":"Chen-Huan Chiang, S. Gupta","doi":"10.1109/ICCAD.1997.643568","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643568","url":null,"abstract":"A built-in self-test (BIST) methodology to test system backplanes by using BIST functionality in each of its constituent boards is presented. Since the configurations of systems change frequently, at the system level, the proposed methodology employs a simple test schedule which can be easily changed whenever the system configuration is changed. Since the boards used in such systems are designed for use in a wide variety of systems, the proposed methodology defines the test objectives to be achieved by a board's BIST circuit in terms of the board's edge pin connections, independent of the configurations of the systems in which the board may be used. It is shown that the combination of the proposed test schedule and the availability, on each board in the system, of any BIST circuit that satisfies the proposed test objectives, guarantees safe testing of faults in backplanes. A programmable test architecture and an algorithm to program the architecture to obtain BIST that satisfies the test objectives is also presented. Finally, the applicability and effectiveness of the methodology is demonstrated via its application to multiple configurations of an example system that uses a VME backplane.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130629289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Minimum area retiming with equivalent initial states 具有等效初始状态的最小面积重定时

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643523

N. Maheshwari, S. Sapatnekar

引用次数: 17

Timing analysis based on primitive path delay fault identification 基于原始路径延迟故障识别的时序分析

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643405

M. Sivaraman, A. Strojwas

{"title":"Timing analysis based on primitive path delay fault identification","authors":"M. Sivaraman, A. Strojwas","doi":"10.1109/ICCAD.1997.643405","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643405","url":null,"abstract":"We present a novel timing analysis mechanism which is based on identifying primitive path delay faults (primitive PDFs) in a circuit. We show that this approach gives the exact maximum delay of the circuit under the floating mode of operation assumption. Our timing analysis approach provides a framework where component delay correlations and signal correlations arising from fabrication process, signal propagation, and signal interaction effects can be handled very accurately. Under these effects, timing analysis using previously reported floating mode timing analyzers, e.g., viability, TrueD-F etc., is very pessimistic. Our timing analysis approach based on primitive PDF identification is also more efficient than conventional floating mode path sensitization analysis mechanisms in situations where critical paths need to be re-identified due to component delay speedup (e.g., postlayout delay optimization). We demonstrate the applicability of our timing analysis approach for a variety of benchmark circuits, and demonstrate the pessimism of conventional floating mode timing analysis approaches in accounting for signal propagation effects.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122951245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4