Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005.最新文献_第2页

Interaction of redistribution traces with on-wafer interconnects in memory chip packaging 存储芯片封装中再分布轨迹与晶圆上互连的相互作用

Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005. Pub Date : 2005-05-10 DOI: 10.1109/SPI.2005.1500936

M. Gospodinova, M.F. Ktata, J. Koellermeyer, G. Nan, M. Vogl, J. Thomas

引用次数: 0

A CMOS compatible process for improved RF performance on highly doped substrates 一种在高掺杂基板上改善射频性能的CMOS兼容工艺

Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005. Pub Date : 2005-05-10 DOI: 10.1109/SPI.2005.1500935

L. Fernández, U. Arz, D. Schubert, E. Berenschot, R. Wiegerink, J. Flokstra

{"title":"A CMOS compatible process for improved RF performance on highly doped substrates","authors":"L. Fernández, U. Arz, D. Schubert, E. Berenschot, R. Wiegerink, J. Flokstra","doi":"10.1109/SPI.2005.1500935","DOIUrl":"https://doi.org/10.1109/SPI.2005.1500935","url":null,"abstract":"In this paper we present a CMOS compatible process for CMOS-grade wafers in order to create specific areas where radio frequency (RF) devices can be implemented without the high losses associated to this substrate. The process is based on refilling of deep trenches, which allows the local replacement of the silicon substrate by silicon nitride, which has very good RF properties (tan /spl delta/ = 5-9 10/sup -4/). The trenches are in the order of 30 /spl mu/m deep and 2 /spl mu/m wide, leaving a space of 2 /spl mu/m in between where the silicon still remains. In this way, half of the lossy substrate is replaced by silicon nitride. We present measurement results which indicate that the RF performance of CMOS-grade wafers can be significantly improved, as well as a careful study of the most relevant fabrication parameters and the consequences for the final RF performance of the substrate. An additional advantage of this new technique is the possibility of using it as a pre-CMOS process, thus allowing monolithic integration of CMOS electronics and RF and microwave components.","PeriodicalId":182291,"journal":{"name":"Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005.","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133599505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Electromagnetic interference self-learning toolkit in switched-mode power supplies 开关电源电磁干扰自学工具包

Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005. Pub Date : 2005-05-10 DOI: 10.1109/SPI.2005.1500947

W. Khan-ngern, V. Tarateeraseth, J. Arthitthang, Jakgree Wongmuang, Therasak Sompanchen, Werachat, Wittaya Tasri

引用次数: 2

Model-order reduction of VLSI circuit interconnects via a Laguerre representation 通过拉盖尔表示的VLSI电路互连的模型阶数降低

Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005. Pub Date : 2005-05-10 DOI: 10.1109/SPI.2005.1500914

M. Telescu, N. Tanguy, P. Bréhonnet, P. Vilbé, Léon-Claude, Calvez, Fabrice Huret

{"title":"Model-order reduction of VLSI circuit interconnects via a Laguerre representation","authors":"M. Telescu, N. Tanguy, P. Bréhonnet, P. Vilbé, Léon-Claude, Calvez, Fabrice Huret","doi":"10.1109/SPI.2005.1500914","DOIUrl":"https://doi.org/10.1109/SPI.2005.1500914","url":null,"abstract":"The VLSI (very large scale integration) industry has the tendency to decrease circuit size, increase speed, assuring ever lower energy consumption and ever higher integration density of analogical components accompanied by digital blocks. With this tendency circuit designers are faced with a new challenge: the analysis and modeling of logical and analogical signals propagating between two circuit points. The search for high speed applications makes the effects of interconnects, usually neglected in the past, an important issue; noise, delay, distortion, reflections and cross talk are just some of these effects. High integration density, miniaturization, high working frequencies are three great factors which prevent interconnects to be considered small independent circuits. Thus, simulation becomes a rather difficult task. Still, wouldn't it be possible to replace complete interconnect equivalent circuits by simpler and more flexible models. Our new model-order reduction technique is mainly based on the use of the Laguerre representation and a simple operator used to generate an approximation base.","PeriodicalId":182291,"journal":{"name":"Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005.","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117118134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Impact of on-die decoupling on the core and IO supplies of high performance microprocessors 芯片上解耦对高性能微处理器内核和IO供应的影响

Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005. Pub Date : 2005-05-10 DOI: 10.1109/SPI.2005.1500887

T. Rahal-Arabi, G. Ji, G. Taylor

引用次数: 0

A 3D miniaturization method for low impedance designs 低阻抗设计的三维小型化方法

Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005. Pub Date : 2005-05-10 DOI: 10.1109/SPI.2005.1500902

S.R. Banerjee, R. F. Drayton

引用次数: 2

3D frequency-dependent RLC elements extraction by full wave analysis: identification of the return current paths in complex power and ground grids of high speed VLSI circuits 基于全波分析的三维频率相关RLC元件提取:高速VLSI电路复杂电源和接地网中返回电流路径的识别

Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005. Pub Date : 2005-05-10 DOI: 10.1109/SPI.2005.1500929

Y. Quéré, T. Le Gouguec, P. Martin, D. Le Berre, F. Huret, L. David, C. Cregut

引用次数: 5

Computation of signal-threshold crossing times 信号阈值穿越次数的计算

Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005. Pub Date : 2005-05-10 DOI: 10.1109/SPI.2005.1500937

A. Ligocka, W. Bandurski

引用次数: 0

Rational modeling of spectral data using orthonormal vector fitting 利用正交矢量拟合对光谱数据进行合理建模

Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005. Pub Date : 2005-05-10 DOI: 10.1109/SPI.2005.1500915

D. Deschrijver, T. Dhaene

引用次数: 42

Part II. Experiments. Signal propagation without distortion on lossy transmission lines having frequency dependent parameters 第二部分。实验。在具有频率相关参数的有损耗传输线上无失真的信号传播

Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005. Pub Date : 2005-05-10 DOI: 10.1109/SPI.2005.1500894

R. Flake, J. Biskup

引用次数: 6