I. Kantorovich, V. Drabkin, C. Houghton, J. St Laurent
{"title":"Measurement of power delivery system impedance, current and switching activity on functioning die","authors":"I. Kantorovich, V. Drabkin, C. Houghton, J. St Laurent","doi":"10.1109/SPI.2005.1500888","DOIUrl":"https://doi.org/10.1109/SPI.2005.1500888","url":null,"abstract":"Power delivery system (PDS) noise, current and impedance are major indicators of chip performance. The paper considers an approach in which on-chip impedance measurement is conducted for controlled periodic step-wise computer process. The main difficulty of the approach is current reconstruction. Current can be obtained from measured equivalent conductance of the chip, which can serve as a quantification of chip activity.","PeriodicalId":182291,"journal":{"name":"Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005.","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127128418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Efficient projection based macromodel for interconnect networks","authors":"M. Ma, R. Khazaka","doi":"10.1109/SPI.2005.1500939","DOIUrl":"https://doi.org/10.1109/SPI.2005.1500939","url":null,"abstract":"This paper presents a projection based technique for obtaining reduced order macromodels of large multi-port interconnect networks. The proposed approach uses two levels of reduction and results in macromodels which are typically half the size of those obtained using traditional Krylov methods. The second level of reduction is based on singular value decomposition (SVD), is very simple to implement and can be easily extended to new applications. Examples are shown that demonstrate the accuracy and efficiency of this approach.","PeriodicalId":182291,"journal":{"name":"Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116609120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Return loss in twisted pair cables","authors":"J. Poltz, M. Josefsson, J. Beckett","doi":"10.1109/SPI.2005.1500910","DOIUrl":"https://doi.org/10.1109/SPI.2005.1500910","url":null,"abstract":"Modeling of twisted pair cable (TPC) and simulating return loss (RL) is discussed and verified experimentally. A graphical user interface allows entering cable design data including materials, plating, stranding, twisting, and wire naming. A realistic 3D model of a twisted pair cable is calculated. The resulting model is subsequently analyzed numerically using a combination of finite element and boundary element methods. Extracted, frequency dependent unit parameters of the cable are used to build a chain parameter model. Conditions for chain parameter segmentation are discussed. A 50 meter long four TPC was used to verify simulation results against RL measurement. The measurements were carried out with a vector network analyzer. Both ends of the cable were connected to special fixtures, which were designed to eliminate reflections. Simulation and measurement are plotted in the frequency range of 100 kHz to 1 GHz. Good agreement between simulation and measurement of RL is reported.","PeriodicalId":182291,"journal":{"name":"Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133909050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design, implementation and testing of miniaturized electromagnetic bandgap structures for broadband switching noise mitigation in high-speed printed circuit boards","authors":"S. Shahparnia, O. Ramahi","doi":"10.1109/SPI.2005.1500889","DOIUrl":"https://doi.org/10.1109/SPI.2005.1500889","url":null,"abstract":"A novel concept for ultra-wideband suppression of switching noise in high-speed printed circuit boards (PCBs) is proposed, implemented and tested. This concept consists of using asymmetrical, embedded electromagnetic bandgap (EEBG) structures in conjunction with material with high dielectric constants. The proposed design modifies the classical EEBG structures to achieve a high degree of miniaturization and an unprecedented broadband mitigation of switching noise.","PeriodicalId":182291,"journal":{"name":"Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127366941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Query, T. Gouguec, P. Martin, D. Berre, Fabrice Huret
{"title":"Techniques to reduce mode conversion phenomena in high-speed on chip interconnects","authors":"Y. Query, T. Gouguec, P. Martin, D. Berre, Fabrice Huret","doi":"10.1109/SPI.2005.1500941","DOIUrl":"https://doi.org/10.1109/SPI.2005.1500941","url":null,"abstract":"This paper describes frequency effects of mode conversion in very high-speed VLSI circuits through a set of full-wave simulations. Long on-chip interconnects such as clock nets are concerned by this phenomenon despite conventional shielding techniques. The solutions proposed for mode conversion reduction rely on transposition of design rules used in microwave circuits.","PeriodicalId":182291,"journal":{"name":"Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130101637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Salhi, W. John, G. Sommer, J. Graf, M. Fiedler, H. Reich
{"title":"Test structures for continuous determination of electrical parameters of substrate material up to 79 GHz","authors":"F. Salhi, W. John, G. Sommer, J. Graf, M. Fiedler, H. Reich","doi":"10.1109/SPI.2005.1500945","DOIUrl":"https://doi.org/10.1109/SPI.2005.1500945","url":null,"abstract":"This paper describes the use of line resonator and as well as micro strip line for continuous monitoring of electrical properties of substrate material. On the basis of a high frequency substrate, a method for determination of the electrical material parameter in a frequency range of 5 GHz to at least 79 GHz is presented. On focus are the relative permittivity, /spl epsiv//sub r/, and the dissipation factor, tan/spl delta/. High frequency measurements are compared to simulation results. Finally, the extracted material parameters are presented and discussed. Both methods are compared to each other concerning accuracy and sensitivity.","PeriodicalId":182291,"journal":{"name":"Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005.","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115657917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Chiariello, A. Maffucci, G. Miano, F. Villone, W. Zamboni
{"title":"Signal integrity analysis of high-speed interconnects through a full-wave transmission line model","authors":"A. Chiariello, A. Maffucci, G. Miano, F. Villone, W. Zamboni","doi":"10.1109/SPI.2005.1500893","DOIUrl":"https://doi.org/10.1109/SPI.2005.1500893","url":null,"abstract":"An enhanced transmission line model has been recently proposed by the authors to perform the frequency-domain full-wave analysis of high-speed interconnects operating in non-TEM condition. Here this model is used to investigate the effects of such operating conditions on the time-domain signal waveforms. The interconnects are described by a reduced-order model, obtained by using the vector fitting method to identify its Z-parameters. The time-domain analysis of the performance of some case-studies highlights degradation of the signal, due to the effects of radiation loss and finite-length dispersion. The solution of the ETL model provides useful indications to control such degradation.","PeriodicalId":182291,"journal":{"name":"Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128043957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Demmer, R. Modinger, J. Bauer, F. Ebling, H. Schroder, P. Beil, H. Albrecht, A. Beier, K. Pfeiffer, M. Franke, E. Griese, M. Reuber, J. Kostelnik
{"title":"New generation interconnection technology: printed circuit boards with integrated optical layers","authors":"P. Demmer, R. Modinger, J. Bauer, F. Ebling, H. Schroder, P. Beil, H. Albrecht, A. Beier, K. Pfeiffer, M. Franke, E. Griese, M. Reuber, J. Kostelnik","doi":"10.1109/SPI.2005.1500948","DOIUrl":"https://doi.org/10.1109/SPI.2005.1500948","url":null,"abstract":"The need for high data rate interconnects within computing and telecommunication equipment is continuously rising. As the performance of electrical interconnects is physically limited through the skin effect, optical interconnects can be used to overcome this problem. Within this paper some results achieved in the frame of the German research and development project NeGIT (new generation interconnection technology), focusing on printed circuit boards with integrated optical waveguides are introduced. The waveguides are part of an optical layer which is manufactured by a photolithographic process. Using standard lamination processes the optical layer is combined with electrical FR4-layers and the result is an electrical-optical printed circuit board which shows a sufficiently high thermal resistivity taking into account the manufacturing processes like lamination and soldering. The compound strength as well as the stability of the optical layer properties are good. Apart from the waveguide technology the concept for optical module-to-board coupling is presented.","PeriodicalId":182291,"journal":{"name":"Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005.","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128091124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Behavior macromodels using circuit templates","authors":"C. Kumar","doi":"10.1109/SPI.2005.1500924","DOIUrl":"https://doi.org/10.1109/SPI.2005.1500924","url":null,"abstract":"There has been increasing trend towards serial bus signaling. This migration has been facilitated by increasing encapsulation of signal integrity functions on chip. Such integration, however, has driven up the complexity of traditional I/O driver models extracted from direct layout. Consequently these models perform slower than ever. This performance degradation makes them unsuitable for what if design prototyping. To overcome this shortcoming a new, novel and practical method of generating fast behavior macromodels is proposed. These models are based on known circuit templates. They include adjustable parameters. Particular implementations are realized by tuning the parameters to match the behavior of the template to a reference layout model. Examples of these template based behavior models are shown. The close correlation they achieve to reference models and real world measurements are demonstrated. Additional work is called for. More model templates and standard methods of specifying them are needed. Further work also needs to be done in formal methods of correlating model parameters.","PeriodicalId":182291,"journal":{"name":"Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005.","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122295410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"More effective Krylov subspace construction for smaller EM-based equivalent circuit models","authors":"Pieter Heres, Jan Niehof, W. Schilders","doi":"10.1109/SPI.2005.1500913","DOIUrl":"https://doi.org/10.1109/SPI.2005.1500913","url":null,"abstract":"Although Krylov subspace methods have proved to be useful techniques to reduce the size of linear interconnect models, they suffer from the drawback of redundancy. The size of the models generated by the methods is larger than strictly needed. In this paper we propose a method to reduce this redundancy. The modification requires only minor extra computational effort and makes Krylov subspace methods significantly more efficient. Two examples are given as a demonstration and validation of the proposed method. We show that with the new method models can be generated which are approximately 25% smaller in size and 50% faster in simulation time.","PeriodicalId":182291,"journal":{"name":"Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127754748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}