{"title":"Association analysis of significant frequent colossal itemsets mined from high dimensional datasets","authors":"Manjunath K. Vanahalli, Nagamma Patil","doi":"10.1109/UPCON.2016.7894662","DOIUrl":"https://doi.org/10.1109/UPCON.2016.7894662","url":null,"abstract":"Bioinformatics has contributed to a different form of datasets called as high dimensional datasets. The high dimensional datasets are characterized by a large number of features and a small number of samples. The traditional algorithms expend most of the running time in mining large number of small and mid-size items which does not enclose valuable and significant information. The recent research focused on mining large cardinality itemsets called as colossal itemsets which are significant to many applications, especially in the field of bioinformatics. The existing frequent colossal itemset mining algorithms are unsuccessful in discovering complete set of significant frequent colossal itemsets. The mined colossal itemsets from existing algorithms provide erroneous support information which affects association analysis. Mining significant frequent colossal itemsets with accurate support information helps in attaining a high-level accuracy of association analysis. The proposed work highlights a novel pre-processing technique and bottom-up row enumeration algorithm to mine significant frequent colossal itemsets with accurate support information. A novel pre-processing technique efficiently utilizes minimum support threshold and minimum cardinality threshold to prune irrelevant samples and features. The experiment results demonstrate that the proposed algorithm has high accuracy over existing algorithms. Performance study indicates the efficiency of the pre-processing technique.","PeriodicalId":151809,"journal":{"name":"2016 IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics Engineering (UPCON)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128800832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Application of genetic algorithm as feature selection technique in development of effective fault prediction model","authors":"L. Kumar, S. Rath","doi":"10.1109/UPCON.2016.7894693","DOIUrl":"https://doi.org/10.1109/UPCON.2016.7894693","url":null,"abstract":"Prediction of faults in a proposed software is helpful in deciding the amount of effort to be given for software development. We observed that, a good number of authors hypothesized that the performance of fault prediction model depends on the source code metrics which are used as input of the model. Feature selection technique is a process of selecting suitable set of source code metrics which may improve the performance of fault prediction model. In this work, genetic algorithm (GA) has been applied as feature selection technique to select the suitable set of source code metrics. This selected set of source code metrics are used as requisite input data to develop a classifier using five different classification techniques such as logistic regression, extreme learning machine, support vector machine (SVM) with three different kernel functions (linear, polynomial, and radial basis kernel functions) in order to predict the faulty and non-faulty classes. In this study, we propose a cost evaluation framework to perform cost based analysis for evaluating the effectiveness of fault prediction model. We perform experiments on thirty number of Java Open Source projects. From the obtained results, it is observed that the model developed using selected set of source code metrics obtained better result as compared to all metrics. From costs analysis framework, it is observed that the developed fault prediction model is best suitable for software with % of faulty classes less than the threshold value depending on fault identification efficiency (low-46.44%, median-45.37%, and high-36.63%).","PeriodicalId":151809,"journal":{"name":"2016 IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics Engineering (UPCON)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127451682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An analytical gate tunneling current model of Re-S/D SOI MOSFETs","authors":"P. Tiwari, Arun Kumar, Dipankar Talukdar","doi":"10.1109/UPCON.2016.7894619","DOIUrl":"https://doi.org/10.1109/UPCON.2016.7894619","url":null,"abstract":"This paper presents an analytical direct gate tunneling current model of recessed-source/drain(Re-S/D) SOI MOSFET. The gate tunneling current behavior has been analyzed by varying different parameters like gate insulator thickness and drain to source voltage. The gate tunneling current has been investigated with the effect of high-k dielectric constant. 2D ATLAS tool has been used to validate the model results.","PeriodicalId":151809,"journal":{"name":"2016 IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics Engineering (UPCON)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121671987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. M. Kumar, M. Naresh, N. Singh, Ashutosh Kumar Singh
{"title":"A passive islanding detection approach for distributed generation using rate of change of negative sequence voltage and current","authors":"K. M. Kumar, M. Naresh, N. Singh, Ashutosh Kumar Singh","doi":"10.1109/UPCON.2016.7894679","DOIUrl":"https://doi.org/10.1109/UPCON.2016.7894679","url":null,"abstract":"In this paper a new passive islanding detection technique is proposed for distributed generation using rate of change of negative sequence voltage and current. The proposed technique is based on the voltage and current measurement at targeted distributed generation (DG). The retrieved voltage and current are converted into symmetrical component through sequence analyzer then rate of change of negative sequence voltage (ROCONSV) and rate of change of negative sequence current (ROCONSC) are calculated for islanding detection. ROCONSV and ROCONSC are tested for different active power mismatching and work effectively even power imbalance is less than 15%. The proposed technique detects islanding very fast less than one cycle. This technique is efficient and free from non detection zone (NDZ).","PeriodicalId":151809,"journal":{"name":"2016 IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics Engineering (UPCON)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114709607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Compact planar rectangular monopole antenna for Bluetooth and UWB Applications","authors":"S. Bhaskar, Rajveer S. Brar, A. Singh","doi":"10.1109/UPCON.2016.7894640","DOIUrl":"https://doi.org/10.1109/UPCON.2016.7894640","url":null,"abstract":"In this article a novel slot loading technique is proposed for integrating Bluetooth band to UWB antenna. The presented coplanar waveguide (CPW) fed rectangular-shaped monopole antenna has symmetrical meandered slots on ground plane. The proposed dual band antenna operates at 2.4–2.5 GHz for WLAN/Bluetooth band and 3.5–10.9 GHz for UWB band. The antenna has a compact electrical size of 0.12λ<inf>0</inf> × 0.19λ<inf>0</inf> × 0.01λ<inf>0</inf> where λ<inf>0</inf> is wavelength at 2.4 GHz. The proposed antenna exhibits appreciable gain, omnidirectional and doughnut-shape radiation pattern in H-plane and E plane respectively, for entire operating bandwidth. The designed antenna exhibits satisfactory performance in time domain analysis with group delay less than 1.5 ns for obtained UWB band. Finally, a prototype is fabricated and measured results are in close agreement with simulated results.","PeriodicalId":151809,"journal":{"name":"2016 IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics Engineering (UPCON)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116735612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Class partition approach for software effort estimation using support vector machine","authors":"Anurag Tiwari, Amrita Chaturvedi","doi":"10.1109/UPCON.2016.7894732","DOIUrl":"https://doi.org/10.1109/UPCON.2016.7894732","url":null,"abstract":"Software effort estimation consists of those procedures and activities which help to predict most accurate development effort as well as cost of a software product. After analyzing various proposed concept and theories regarding this we tried to give a new concept which works over partition of a data set. The partition procedure depends over the correlation of input features as well as output features. This algorithm is a generic concept which can be useful in other fields also. Previously proposed models and theories depend on the detection and prediction methodologies. In detection process, developers try to find out loopholes in the prior proposed models while in prediction model they try to develop a new theory that mitigates those loopholes. In our proposed approach we work over a mathematical model that can be a replacement of a well-known data mining algorithm K-NN (K nearest neighbor), which uses clusters for classification. Our proposed methodology is based on feature selection. This feature selection process is based on correlation coefficient that can be defined by the user. After feature selection, we tried to achieve the rate of change of the target attribute with respect to the other attributes. We have classified the data vectors according to the rate of change of target value (Effort) and attributes obtained after feature selection. Target value (Effort) will be fixing for whole processing. Finally we applied regression to obtain a mathematical model for the corresponding class.","PeriodicalId":151809,"journal":{"name":"2016 IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics Engineering (UPCON)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122328302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"F-shaped monopole based MIMO antenna for WLAN applications","authors":"B. V. Singh, M. Agarwal, M. K. Meshram","doi":"10.1109/UPCON.2016.7894718","DOIUrl":"https://doi.org/10.1109/UPCON.2016.7894718","url":null,"abstract":"In this paper, A triple band multiple-input-multiple-output (MIMO) antenna array is proposed for a conveyable wireless device for WLAN applications (band 1: 2.4 – 2.484 GHz, band 2: 5.15 – 5.35 GHz, and band 3: 5.725 – 5.825 GHz). The proposed antenna array consists of two monopole antenna components which are separated by approximately one-tenth of the wavelength of the lower frequency band (2.45 GHz). In order to reduce the radiator size, it is designed in the shape of F and the two branches of F are responsible for producing the designated frequency bands. The resonance centered at 2.45 GHz is covering band 1 while the resonance centered at 5.4 GHz is covering band 2 and band 3. Both the elements are the mirror image of each other over a partial ground plane with FR-4 as substrate. Furthermore, the optimal coupling between two elements is achieved by cutting a dumbbell shaped cut-out within the ground plane between the antenna components. The measure of proposed antenna is only 35 × 40 × 1.6 mm3. In addition, the characteristic of small size, nearly omnidirectional coverage and good diversity performance make the proposed MIMO antenna suitable to the mobile WLAN applications.","PeriodicalId":151809,"journal":{"name":"2016 IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics Engineering (UPCON)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129639434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improved three Dimensional Turbo Code using Superposition Modulation techniques: Extension to WiMAX system","authors":"S. Banerjee, S. Chattopadhyay, Ananya Dey","doi":"10.1109/UPCON.2016.7894671","DOIUrl":"https://doi.org/10.1109/UPCON.2016.7894671","url":null,"abstract":"Communication systems need for regeneration of consistent information by controlling errors in a noisy environment. This is accomplished by incorporating suitable forward error correcting coding techniques into the system. In this context, Turbo Code (TC) is regarded as one of the high-performance forward error correcting codes whose BER performances tends to the “Shannon limit”. An advanced form of Turbo Code (TC) named as 3-Dimensional Turbo Code (3D-TC) has been appeared as a thought-provoking investigation zone in recent past. Meanwhile an exhaustive research has been carried out on Superposition Modulation (SM) techniques in which switching from bit to symbols is occurred using non-bijective mapping method. Considering the above facts, a novel SM based 3D-TC has been suggested in this paper to enrich the Bit Error Rate (BER) act ominously by choosing right combination of generator polynomial for each constituent encoder as well as interleavers. The effectiveness of the projected code has also been evaluated by comparing its BER performance with other existing codes in WiMAX system under different fading channel conditions.","PeriodicalId":151809,"journal":{"name":"2016 IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics Engineering (UPCON)","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127851913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Vanshika Jindal, Laxman Singh, Prem Prakash Dudi, S. Choudhuri
{"title":"Operation of Induction Motor in Vector Controlled Mode with variation in Speed Controller logic: A comparative study","authors":"Vanshika Jindal, Laxman Singh, Prem Prakash Dudi, S. Choudhuri","doi":"10.1109/UPCON.2016.7894708","DOIUrl":"https://doi.org/10.1109/UPCON.2016.7894708","url":null,"abstract":"This paper presents a comparative study of drive dynamics of a Vector Controlled Induction Motor Drive (VCIMD) by varying the Speed Controller logic to introduce accuracy and retain simplicity. The analysis is carried out in MATLAB environment using Sim Power System (SPS) and Simulink toolboxes in Discrete Time Frame (DTF) for a fixed switching frequency. The strategy of indirect vector Control is adopted for Current Controlled (CC) Voltage Source Inverter (VSI) fed squirrel cage induction motor. Simulation of the drive response under various operating conditions such as starting, reversal and load perturbation respectively are analysed. Effects of variation in speed controller logic on the dynamic response of the VCIMD are compared from application point of view.","PeriodicalId":151809,"journal":{"name":"2016 IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics Engineering (UPCON)","volume":"25 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131520164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ISOGI-Q based control algorithm for single stage grid tied SPV system","authors":"Bhim Singh, Priyank Shah, Ikhlaq Hussain","doi":"10.1109/UPCON.2016.7894705","DOIUrl":"https://doi.org/10.1109/UPCON.2016.7894705","url":null,"abstract":"This paper deals with a single stage solar photovoltaic (SPV) array tied with a three phase grid by using an improved second order generalized integrator quadrature signal generator (ISOGI-QSG) based control algorithm to improve power quality of the grid. The maximum point power tracking (MPPT) is achieved by using an incremental conductance method. The incremental conductance MPPT method is effective to extract maximum power from a SPV array as well as to regulate the DC link voltage. ISOGI-QSG based control algorithm is robust and enhances the power quality in terms of load balancing, noise elimination and power factor correction (PFC) very effectively. Having D-STATCOM capabilities of SPV based system is useful to supply the active power to grid as well as to loads. The control algorithm is verified on proposed system topology and obtained responses are found satisfactory and total harmonic distortion (THD) of source currents within standard limit.","PeriodicalId":151809,"journal":{"name":"2016 IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics Engineering (UPCON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114144574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}