2023 IEEE 24th Latin American Test Symposium (LATS)最新文献_第3页

Low cost external serial interface watchdog for SoCs and FPGAs automatic characterization tests 低成本的外部串行接口看门狗，用于soc和fpga的自动特性测试

2023 IEEE 24th Latin American Test Symposium (LATS) Pub Date : 2023-03-21 DOI: 10.1109/LATS58125.2023.10154486

P. Bernardi, Gabriele Filipponi, T. Foscale, Giorgio Insinga

{"title":"Low cost external serial interface watchdog for SoCs and FPGAs automatic characterization tests","authors":"P. Bernardi, Gabriele Filipponi, T. Foscale, Giorgio Insinga","doi":"10.1109/LATS58125.2023.10154486","DOIUrl":"https://doi.org/10.1109/LATS58125.2023.10154486","url":null,"abstract":"Manufacturers must characterize their design deeply when designing and producing devices like FPGAs and SoCs. Information collected through simulation and physical experiments is the primary data source for manufacturers that can then decide the optimal working ranges of multiple critical parameters such as operating voltage, frequency, temperatures, etc. With complex devices such as SoCs, and FPGAs with integrated PLLs and voltage regulators, each combination of voltage and frequency can be checked by communicating the desired parameters to the DUT, running a functional test, and observing the results. However once the ATE sends the desired parameters to the DUT through SPI or other serial interfaces, the DUT may freeze and stop to accept new commands entirely. This is particularly problematic for targeted characterization that may include a minimal number of boards and DUTs and where the ATE may simply be a simple laptop without any automatic DUT reset capabilities. This paper presents an external serial communication watchdog designed using an ESP32-based board. Our watchdog can detect the communications coming from the ATE, monitor the answers from the DUT, and restart it through power cycling in case of freezing.","PeriodicalId":145157,"journal":{"name":"2023 IEEE 24th Latin American Test Symposium (LATS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133909291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analyzing Side-Channel Attack Vulnerabilities at RTL RTL侧信道攻击漏洞分析

2023 IEEE 24th Latin American Test Symposium (LATS) Pub Date : 2023-03-21 DOI: 10.1109/LATS58125.2023.10154497

X. Lai, M. Jenihhin

引用次数: 0

Organizing and Sponsorship 组织及赞助

2023 IEEE 24th Latin American Test Symposium (LATS) Pub Date : 2023-03-21 DOI: 10.1109/lats58125.2023.10154499

引用次数: 0

Evaluating a New RRAM Manufacturing Test Strategy 评价一种新的RRAM制造测试策略

2023 IEEE 24th Latin American Test Symposium (LATS) Pub Date : 2023-03-21 DOI: 10.1109/LATS58125.2023.10154503

T. Copetti, A. Castelnuovo, T. Gemmeke, L. Bolzani

{"title":"Evaluating a New RRAM Manufacturing Test Strategy","authors":"T. Copetti, A. Castelnuovo, T. Gemmeke, L. Bolzani","doi":"10.1109/LATS58125.2023.10154503","DOIUrl":"https://doi.org/10.1109/LATS58125.2023.10154503","url":null,"abstract":"Memristive devices represent a promising candidate to complement the CMOS technology due to their ability to overcome CMOS device technology limits as well as to implement not only memory but also computing elements. These characteristics make the implementation of emerging applications with strict constraints in terms of performance, area and power consumption possible. However, the adoption of these novel devices depends on being able to guarantee their quality after manufacturing. High-volume manufacturing tests pose significant challenges in terms of fault detection capability, test time as well as implementation overheads. In this context, this paper proposes a new implementation Design-for-Testability (DfT) strategy to test Resistive Random Access Memories (RRAMs). A case study based on a RRAM was implemented using the 28nm TSMC technology library and validated through electrical simulations. The new DfT strategy was evaluated with respect to its ability to detect unique and conventional faults. Finally, the paper presents a discussion about the introduced overheads and compares the proposed approach with state-of-the-art related to RRAM manufacturing test strategies.","PeriodicalId":145157,"journal":{"name":"2023 IEEE 24th Latin American Test Symposium (LATS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114378850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Fault Injection Framework for AI Hardware Accelerators 人工智能硬件加速器的故障注入框架

2023 IEEE 24th Latin American Test Symposium (LATS) Pub Date : 2023-03-21 DOI: 10.1109/LATS58125.2023.10154505

Salvatore Pappalardo, A. Ruospo, Ian O’Connor, B. Deveautour, Ernesto Sánchez, A. Bosio

引用次数: 0

LUT-based Arithmetic Circuit Approximation with Formal Guarantee on Worst Case Relative Error 基于lut的最坏情况相对误差形式保证算法电路逼近

2023 IEEE 24th Latin American Test Symposium (LATS) Pub Date : 2023-03-21 DOI: 10.1109/LATS58125.2023.10154494

Pooja Choudhary, Lava Bhargava, M. Fujita, Virendra Singh

引用次数: 1

Holistic IJTAG-based External and Internal Fault Monitoring in UAVs 基于ijtag的无人机内外故障整体监测

2023 IEEE 24th Latin American Test Symposium (LATS) Pub Date : 2023-03-03 DOI: 10.1109/LATS58125.2023.10154489

Foisal Ahmed, M. Jenihhin

{"title":"Holistic IJTAG-based External and Internal Fault Monitoring in UAVs","authors":"Foisal Ahmed, M. Jenihhin","doi":"10.1109/LATS58125.2023.10154489","DOIUrl":"https://doi.org/10.1109/LATS58125.2023.10154489","url":null,"abstract":"Cyber-Physical Systems (CPSs), such as Unmanned Aerial Vehicles (UAVs), use System-on-Chip (SoC) based computing platforms to perform multiple complex tasks in safety-critical applications that require a highly dependable operation. Due to continuous technological manufacturing miniaturization SoCs face a wide spectrum of chip-level reliability issues such as aging, soft and hard errors during the operational lifetime of a UAV. In addition, external (off-chip) faults in the sensors, actuators, and motors are another cause of UAV failures. While existing works examine either on-chip faults (internal) or sensors/actuators faults (external) separately, this research proposes a UAV health monitoring infrastructure considering both external and internal faults holistically. The proposed method relies on the IEEE 1687 standard (IJTAG) and employs on-chip embedded instruments as health monitors to instantly access external and internal sensor data. Experimental results for functional simulation of a real-life case-study design demonstrate both types of fault detection by serving only three clock cycles and the localization process using 16 and 30 clock cycles for the case of single and double faults, respectively.","PeriodicalId":145157,"journal":{"name":"2023 IEEE 24th Latin American Test Symposium (LATS)","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114550553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0