2023 IEEE 24th Latin American Test Symposium (LATS)最新文献_第2页

Invited Paper: A Holistic Fault Injection Platform for Neuromorphic Hardware 邀请论文:神经形态硬件的整体故障注入平台

2023 IEEE 24th Latin American Test Symposium (LATS) Pub Date : 2023-03-21 DOI: 10.1109/LATS58125.2023.10154482

Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, J. Joseph, L. Bolzani, R. Leupers

{"title":"Invited Paper: A Holistic Fault Injection Platform for Neuromorphic Hardware","authors":"Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, J. Joseph, L. Bolzani, R. Leupers","doi":"10.1109/LATS58125.2023.10154482","DOIUrl":"https://doi.org/10.1109/LATS58125.2023.10154482","url":null,"abstract":"Logic-in-memory (LIM) is a promising flavor of the computing-in-memory (CIM) paradigm that utilizes memristive crossbar arrays to execute logic gates, resulting in high per-formance and energy efficiency. Binary neural networks (BNNs) can particularly benefit from LIM due to their massive parallel execution of binary logic gates. However, the impact of faults on BNNs accelerated with LIM has yet to be thoroughly investigated. To address this gap, we developed two distinct fault injection frameworks able to provide insights into the impact of different types of faults on the behavior of LIM. On the one hand, X-Fault aims to evaluate the impact of different faults that can affect crossbar arrays after manufacturing. On the other hand, FLIM allows for evaluating in-field faults on LIM. While both frameworks excel at their respective abstraction level, the complexity of neuromorphic systems requires a comprehensive fault analysis to grasp the fundamental impact stemming from the memristor to the BNN. Hence, we propose X-FLIM, a holistic fault injection platform capable of executing full-fledged BNNs on LIM while injecting in-field faults at the memristor and application level.","PeriodicalId":145157,"journal":{"name":"2023 IEEE 24th Latin American Test Symposium (LATS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128997746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A New Defect Model due to a Dust Particle Affecting the Fingers of FinFET Logic Gates 一种新的粉尘颗粒影响FinFET逻辑门指的缺陷模型

2023 IEEE 24th Latin American Test Symposium (LATS) Pub Date : 2023-03-21 DOI: 10.1109/LATS58125.2023.10154490

V. Champac, Freddy Forero, M. Renovell, Leonardo Miceli

引用次数: 0

Feature Selection for Cost Reduction In MCU Performance Screening 降低MCU性能筛选成本的特征选择

2023 IEEE 24th Latin American Test Symposium (LATS) Pub Date : 2023-03-21 DOI: 10.1109/LATS58125.2023.10154495

N. Bellarmino, R. Cantoro, M. Huch, T. Kilian, Ulf Schlichtmann, Giovanni Squillero

{"title":"Feature Selection for Cost Reduction In MCU Performance Screening","authors":"N. Bellarmino, R. Cantoro, M. Huch, T. Kilian, Ulf Schlichtmann, Giovanni Squillero","doi":"10.1109/LATS58125.2023.10154495","DOIUrl":"https://doi.org/10.1109/LATS58125.2023.10154495","url":null,"abstract":"In safety-critical applications, microcontrollers must satisfy strict quality constraints and performances in terms of $F_{max}$, that is, the maximum operating frequency. It has been demonstrated that data extracted from on-chip ring oscillators, the so-called speed monitors, can model the $F_{max}$ of integrated circuits using machine learning models. Those models are suitable for the performance screening process, and they use speed monitors are features, while the target is the Fmax. But if the number of features used for building a machine learning model is huge, the risk of over-fitting or curse of dimensionality is high, leading to a high generalization error. Also, devices with a high number of ring-oscillator are costly to be produced. This paper copes with supervised feature selection in microcontroller performance screening during the early phase of prototyping and presents methodologies to reduce the number of monitors needed to build efficient machine learning models without losing in accuracy. We propose a methodology to rank features according to their importance in the performance prediction, able to extract a subset of them drastically reduced in size, but still able to well solve the underlying task. Experiments showed that the chosen subset of features leads to simpler ML models that can achieve lower prediction error, reducing overfitting. This permits avoiding inserting the full set of sensors in the final product, with a huge saving of money and physical space in the silicon.","PeriodicalId":145157,"journal":{"name":"2023 IEEE 24th Latin American Test Symposium (LATS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130706410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Effect of Vth shifting in CMOS Transistors under radiation conditions when applying OBT: A case study 辐射条件下应用OBT对CMOS晶体管v值漂移的影响:一个案例研究

2023 IEEE 24th Latin American Test Symposium (LATS) Pub Date : 2023-03-21 DOI: 10.1109/LATS58125.2023.10154481

P. Petrashin, W. Lancioni, Agustin Laprovitta, F. Dualibe, J. Castagnola

引用次数: 0

Analyzing the Architectural Impact of Transient Fault Effects in SFUs of GPUs gpu交换板瞬态故障效应对体系结构的影响分析

2023 IEEE 24th Latin American Test Symposium (LATS) Pub Date : 2023-03-21 DOI: 10.1109/LATS58125.2023.10154504

J. E. R. Condia, Juan-David Guerrero-Balaguera, Edward Javier Patiño Nuñez, Robert Limas Sierra, M. Reorda

{"title":"Analyzing the Architectural Impact of Transient Fault Effects in SFUs of GPUs","authors":"J. E. R. Condia, Juan-David Guerrero-Balaguera, Edward Javier Patiño Nuñez, Robert Limas Sierra, M. Reorda","doi":"10.1109/LATS58125.2023.10154504","DOIUrl":"https://doi.org/10.1109/LATS58125.2023.10154504","url":null,"abstract":"11This work has been supported by the National Resilience and Recovery Plan (PNRR) through the National Center for HPC, Big Data and Quantum Computing.Graphics Processing Units (GPUs) are crucial in modern safety-critical systems to implement complex and dense algorithms, so their reliability plays an essential role in several domains (e.g., automotive and autonomous machines). In fact, reliability evaluations in GPUs and their internal units are of special interest by their high parallelism and to identify vulnerable structures. In particular, Special Function Unit (SFU) cores, inside GPUs, are highly used in multimedia, scientific computing, and the training of neural networks. However, reliability evaluations in SFUs have remained highly unexplored. This work evaluates the impact of transient faults in the hardware structures of SFUs for GPUs. We focus on evaluating and analyzing two SFU architectures (‘fused’ and ‘modular’) and their relations to energy, area, and reliability impact on GPU workloads. The evaluation resorts to a fine-grain analysis with experiments using an RTL open-source GPU (FlexGripPlus) instrumented with both SFUs. The experimental results on both SFU architectures indicate that modular SFUs are less vulnerable to transient faults (in up to 47% for the analyzed workloads) and are more power efficient (in up to 36.6%) but require additional cost in terms of area (about 27%) in comparison with a fused SFU architecture (base for commercial devices), which seems more vulnerable to faults, but is area efficient.","PeriodicalId":145157,"journal":{"name":"2023 IEEE 24th Latin American Test Symposium (LATS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121523176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Blockchain Applied In Decentralization of Ground Stations To Educational Nanosatellites 区块链在教育纳米卫星地面站去中心化中的应用

2023 IEEE 24th Latin American Test Symposium (LATS) Pub Date : 2023-03-21 DOI: 10.1109/LATS58125.2023.10154485

Edilson Filho, J. Silveira, César Marcon

{"title":"Blockchain Applied In Decentralization of Ground Stations To Educational Nanosatellites","authors":"Edilson Filho, J. Silveira, César Marcon","doi":"10.1109/LATS58125.2023.10154485","DOIUrl":"https://doi.org/10.1109/LATS58125.2023.10154485","url":null,"abstract":"Space has increasingly attracted the attention of governments, large industries, and universities. One of the most popular strategies in recent years has been the adoption of nanosatellites to fulfill different missions, which can work alone or in constellations. Universities stand out among the agents launching nanosatellites, with more than 600 launches until 2022. Given the growth of entities that control space missions, it is necessary to implement new methods for communication between control and satellite to accelerate data transmission and provide a high-security degree. Our work proposes a consortium archi-tecture between Ground Stations (GSs) so that a GS as a Service (GSaaS) works with low cost, reliability, and resource sharing. We simulated a nanosatellite mission in Low Earth Orbit (LEO) with MATLAB to obtain the parameters of average communication time, propagation loss, and at which angles the communication would be most affected by atmospheric phenomena. Then, we implement business rules for communication between GS and satellites using smart contract concepts. We set up a blockchain to provide the decentralization infrastructure and created a web service to provide a communication API between nanosatellite and blockchain. We simulated the firmware update process, showing that the nanosatellite took around 20 minutes to request all 32-byte fragments of 301 Kb firmware. Considering the time interval that the communication window between GS and nanosatellite remains active, the entire firmware transmission takes two to three communication slots. However, the transmission time is drastically reduced in a scenario with two or more GSs. Furthermore, the GSaaS decentralized infrastructure allows the consortium of GSs to communicate agnostically with the satellites, preserving firmware privacy due to the cryptography used in blockchain transactions","PeriodicalId":145157,"journal":{"name":"2023 IEEE 24th Latin American Test Symposium (LATS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128331267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Silent Error Corruption: The New Reliability and Test Challenge 无声错误损坏:新的可靠性和测试挑战

2023 IEEE 24th Latin American Test Symposium (LATS) Pub Date : 2023-03-21 DOI: 10.1109/LATS58125.2023.10154487

A. Singh

引用次数: 0

On the integration and hardening of Software Test Libraries in Real-Time Operating Systems 实时操作系统中软件测试库的集成与加固

2023 IEEE 24th Latin American Test Symposium (LATS) Pub Date : 2023-03-21 DOI: 10.1109/LATS58125.2023.10154492

F. Angione, P. Bernardi, R. Cantoro, Nicola Di Gruttola Giardino, D. Piumatti, M. Reorda, D. Appello, V. Tancorre

{"title":"On the integration and hardening of Software Test Libraries in Real-Time Operating Systems","authors":"F. Angione, P. Bernardi, R. Cantoro, Nicola Di Gruttola Giardino, D. Piumatti, M. Reorda, D. Appello, V. Tancorre","doi":"10.1109/LATS58125.2023.10154492","DOIUrl":"https://doi.org/10.1109/LATS58125.2023.10154492","url":null,"abstract":"The performance and complexity of Automotive System-on-Chip (SoC) have dramatically risen in the last decade thanks to technology scaling and moved to multicore capabilities. As a matter of fact, user requirements and the scenario complex-ity handled by devices are dramatically growing. Therefore, bare-metal safety-critical applications have shifted to a new application paradigm on top of Real-Time Operating Systems (RTOS). Safety standards require runtime self-check procedures the CPU executes from time to time. Such self-test procedures have strict requirements on their execution time and memory foot-print. The aforementioned self-test processes are also known as Software-Based Self Test encapsulated in Software Test Libraries. Following the shift to applications written on top of an RTOS, Software Test Libraries must also be integrated. This paper investigates possible software architectures when integrating Software Test Libraries in RTOSes with their pros e cons. Afterward, some hardening mechanisms are provided to overcome eventual problems in case permanent or transient faults arise. In order to simulate critical conditions, fault injections are performed via debugger in the Software Test Library to investigate their behavior and how they affect the system. Previously developed Software Test Library is integrated into a commercial RTOS called Micrium C OS-III. The fault injection campaign is performed on a real automotive System-on-Chip belonging to the SPC58 family from ST Microelectronics.","PeriodicalId":145157,"journal":{"name":"2023 IEEE 24th Latin American Test Symposium (LATS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116260767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Error Resilient Neuromorphic Systems Using Embedded Predictive Neuron Checks 使用嵌入式预测神经元检查的错误弹性神经形态系统

2023 IEEE 24th Latin American Test Symposium (LATS) Pub Date : 2023-03-21 DOI: 10.1109/LATS58125.2023.10154498

C. Amarnath, A. Chatterjee

{"title":"Error Resilient Neuromorphic Systems Using Embedded Predictive Neuron Checks","authors":"C. Amarnath, A. Chatterjee","doi":"10.1109/LATS58125.2023.10154498","DOIUrl":"https://doi.org/10.1109/LATS58125.2023.10154498","url":null,"abstract":"The reliability of emerging neuromorphic compute fabrics is of great concern due to their widespread use in critical data-intensive applications. Ensuring such reliability is difficult due to the intensity of underlying computations (billions of parameters), errors induced by low power operation and the complex relationship between errors in computations and their effect on network performance accuracy. We study the problem of designing error-resilient neuromorphic systems where errors can stem from: (a) soft errors in computation of matrix-vector multiplications and neuron activations, (b) malicious trojan and adversarial security attacks and (c) effects of manufacturing process variations on analog crossbar arrays that can affect DNN accuracy. The core principle of error detection relies on embedded predictive neuron checks using invariants derived from the statis-tics of nominal neuron activation patterns of hidden layers of a neural network. Algorithmic encodings of hidden neuron function are also used to derive invariants for checking. A key contribution is designing checks that are robust to the inherent nonlinearity of neuron computations with minimal impact on error detection coverage. Once errors are detected, they are corrected using probabilistic methods due to the difficulties involved in exact error diagnosis in such complex systems. The technique is scalable across soft errors as well as a range of security attacks. The effects of manufacturing process variations are handled through the use of compact tests from which DNN performance can be assessed using learning techniques. Experimental results on a variety of neuromorphic test systems: DNNs, spiking networks and hyperdimensional computing are presented.","PeriodicalId":145157,"journal":{"name":"2023 IEEE 24th Latin American Test Symposium (LATS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115506596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Test Aspects of System Health State Monitoring 系统运行状况状态监视的测试方面

2023 IEEE 24th Latin American Test Symposium (LATS) Pub Date : 2023-03-21 DOI: 10.1109/LATS58125.2023.10154480

H. Wunderlich, Hanieh Jafarzadeh, Alexandra Kourfali, N. Lylina, Zahra Paria Najafi-Haghi

引用次数: 0